soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / mainboard / google / kahlee / chromeos.c
blob4b71175519cb5216fbb2a07793ff3a963f353377
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <types.h>
4 #include <vendorcode/google/chromeos/chromeos.h>
5 #include <bootmode.h>
6 #include <boot/coreboot_tables.h>
7 #include <gpio.h>
8 #include <variant/gpio.h>
10 void fill_lb_gpios(struct lb_gpios *gpios)
12 struct lb_gpio chromeos_gpios[] = {
13 {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
14 {-1, ACTIVE_HIGH, 0, "power"},
15 {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
16 "EC in RW"},
19 lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
22 int get_write_protect_state(void)
24 /* Write protect is active low, so invert it here */
25 return !gpio_get(CROS_WP_GPIO);
28 static const struct cros_gpio cros_gpios[] = {
29 CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME),
30 CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME),
32 DECLARE_CROS_GPIOS(cros_gpios);
34 int get_ec_is_trusted(void)
36 /* EC is trusted if not in RW. */
37 return !gpio_get(GPIO_EC_IN_RW);