src/mainboard/google/link/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/pci_ops.h>
   4 #include <northbridge/intel/sandybridge/sandybridge.h>
   5 #include <northbridge/intel/sandybridge/raminit.h>
   6 #include <southbridge/intel/bd82x6x/pch.h>
   7 #include <southbridge/intel/common/gpio.h>
   8 #include "ec/google/chromeec/ec.h"
   9
  10 #include <southbridge/intel/bd82x6x/chip.h>
  11
  12 void mainboard_pch_lpc_setup(void)
  13 {
  14         /* Enable additional 0x200..0x207 for EC */
  15         pci_or_config16(PCH_LPC_DEV, LPC_EN, GAMEL_LPC_EN);
  16 }
  17
  18 void mainboard_late_rcba_config(void)
  19 {
  20         /*
  21          *             GFX    INTA -> PIRQA (MSI)
  22          * D28IP_P3IP  WLAN   INTA -> PIRQB
  23          * D29IP_E1P   EHCI1  INTA -> PIRQD
  24          * D26IP_E2P   EHCI2  INTA -> PIRQF
  25          * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
  26          * D31IP_SMIP  SMBUS  INTB -> PIRQH
  27          * D31IP_TTIP  THRT   INTC -> PIRQA
  28          * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
  29          *
  30          * TRACKPAD                -> PIRQE (Edge Triggered)
  31          * TOUCHSCREEN             -> PIRQG (Edge Triggered)
  32          */
  33
  34         /* Device interrupt pin register (board specific) */
  35         RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
  36                 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
  37         RCBA32(D30IP) = (NOINT << D30IP_PIP);
  38         RCBA32(D29IP) = (INTA << D29IP_E1P);
  39         RCBA32(D28IP) = (INTA << D28IP_P3IP);
  40         RCBA32(D27IP) = (INTA << D27IP_ZIP);
  41         RCBA32(D26IP) = (INTA << D26IP_E2P);
  42         RCBA32(D25IP) = (NOINT << D25IP_LIP);
  43         RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
  44
  45         /* Device interrupt route registers */
  46         DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
  47         DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
  48         DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
  49         DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
  50         DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
  51         DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
  52         DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
  53 }
  54
  55 static unsigned int get_spd_index(void)
  56 {
  57         const int gpio_vector[] = {41, 42, 43, 10, -1};
  58         return get_gpios(gpio_vector);
  59 }
  60
  61 void mainboard_fill_pei_data(struct pei_data *pei_data)
  62 {
  63         /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
  64 }
  65
  66 void mb_get_spd_map(struct spd_info *spdi)
  67 {
  68         /* LINK has 2 channels of memory down */
  69         spdi->addresses[0] = SPD_MEMORY_DOWN;
  70         spdi->addresses[2] = SPD_MEMORY_DOWN;
  71         spdi->spd_index = get_spd_index();
  72 }
  73
  74 void mainboard_early_init(int s3resume)
  75 {
  76         if (!s3resume) {
  77                 /* This is the fastest way to let users know
  78                  * the Intel CPU is now alive.
  79                  */
  80                 google_chromeec_kbbacklight(100);
  81         }
  82 }