soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / mainboard / google / veyron_mickey / bootblock.c
blob261d7e54020471ad9d454fcd9a4e9c5fc35cd910
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/mmio.h>
4 #include <assert.h>
5 #include <bootblock_common.h>
6 #include <delay.h>
7 #include <soc/clock.h>
8 #include <soc/i2c.h>
9 #include <soc/grf.h>
10 #include <soc/pmu.h>
11 #include <soc/rk808.h>
12 #include <soc/spi.h>
13 #include <vendorcode/google/chromeos/chromeos.h>
15 #include "board.h"
17 void bootblock_mainboard_early_init(void)
19 if (CONFIG(CONSOLE_SERIAL)) {
20 assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
21 write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
25 void bootblock_mainboard_init(void)
27 if (rkclk_was_watchdog_reset())
28 reboot_from_watchdog();
30 gpio_output(GPIO(7, A, 0), 1); /* Power LED */
32 /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
33 setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
34 setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
35 assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
36 i2c_init(CONFIG_PMIC_BUS, 400*KHz);
38 /* Slowly raise to max CPU voltage to prevent overshoot */
39 rk808_configure_buck(1, 1200);
40 udelay(175);/* Must wait for voltage to stabilize,2mV/us */
41 rk808_configure_buck(1, 1400);
42 udelay(100);/* Must wait for voltage to stabilize,2mV/us */
43 rkclk_configure_cpu(APLL_1800_MHZ);
45 /* i2c1 for tpm */
46 write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
47 i2c_init(1, 400*KHz);
49 /* spi2 for firmware ROM */
50 write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
51 write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
52 rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
54 setup_chromeos_gpios();