src/mainboard/google/zork/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <amdblocks/acpi.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <device/mmio.h>
   7 #include <acpi/acpi.h>
   8 #include <acpi/acpigen.h>
   9 #include <amdblocks/amd_pci_util.h>
  10 #include <amdblocks/smi.h>
  11 #include <baseboard/variants.h>
  12 #include <boardid.h>
  13 #include <gpio.h>
  14 #include <soc/cpu.h>
  15 #include <soc/pci_devs.h>
  16 #include <soc/platform_descriptors.h>
  17 #include <soc/southbridge.h>
  18 #include <soc/smi.h>
  19 #include <soc/soc_util.h>
  20 #include <amdblocks/acpimmio.h>
  21 #include <variant/ec.h>
  22 #include <variant/thermal.h>
  23 #include <commonlib/helpers.h>
  24
  25 #define METHOD_BACKLIGHT_ENABLE    "\\_SB.BKEN"
  26 #define METHOD_BACKLIGHT_DISABLE   "\\_SB.BKDS"
  27 #define METHOD_MAINBOARD_INI       "\\_SB.MINI"
  28 #define METHOD_MAINBOARD_WAK       "\\_SB.MWAK"
  29 #define METHOD_MAINBOARD_PTS       "\\_SB.MPTS"
  30
  31 /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
  32    accessed via I/O ports 0xc00/0xc01. */
  33
  34 /*
  35  * This controls the device -> IRQ routing.
  36  *
  37  * Hardcoded IRQs:
  38  *  0: timer < soc/amd/common/acpi/lpc.asl
  39  *  1: i8042 <- ec/google/chromeec/acpi/superio.asl
  40  *  2: cascade
  41  *  8: rtc0 <- soc/amd/common/acpi/lpc.asl
  42  *  9: acpi <- soc/amd/common/acpi/lpc.asl
  43  * 12: i8042 <- ec/google/chromeec/acpi/superio.asl
  44  */
  45 static const struct fch_irq_routing fch_irq_map[] = {
  46         { PIRQ_A,       6,              PIRQ_NC },
  47         { PIRQ_B,       13,             PIRQ_NC },
  48         { PIRQ_C,       14,             PIRQ_NC },
  49         { PIRQ_D,       15,             PIRQ_NC },
  50         { PIRQ_E,       15,             PIRQ_NC },
  51         { PIRQ_F,       14,             PIRQ_NC },
  52         { PIRQ_G,       13,             PIRQ_NC },
  53         { PIRQ_H,       6,              PIRQ_NC },
  54
  55         { PIRQ_SCI,     ACPI_SCI_IRQ,   ACPI_SCI_IRQ },
  56         { PIRQ_EMMC,    5,              5 },
  57         { PIRQ_GPIO,    7,              7 },
  58         { PIRQ_I2C2,    10,             10 },
  59         { PIRQ_I2C3,    11,             11 },
  60         { PIRQ_UART0,   4,              4 },
  61         { PIRQ_UART1,   3,              3 },
  62
  63         /* The MISC registers are not interrupt numbers */
  64         { PIRQ_MISC,    0xfa,           0x00 },
  65         { PIRQ_MISC0,   0x91,           0x00 },
  66         { PIRQ_MISC1,   0x00,           0x00 },
  67         { PIRQ_MISC2,   0x00,           0x00 },
  68 };
  69
  70 const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
  71 {
  72         *length = ARRAY_SIZE(fch_irq_map);
  73         return fch_irq_map;
  74 }
  75
  76 static void mainboard_configure_gpios(void)
  77 {
  78         size_t base_num_gpios, override_num_gpios;
  79         const struct soc_amd_gpio *base_gpios, *override_gpios;
  80
  81         base_gpios = baseboard_gpio_table(&base_num_gpios);
  82         override_gpios = variant_override_gpio_table(&override_num_gpios);
  83
  84         gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios,
  85                                           override_num_gpios);
  86 }
  87
  88 static void mainboard_devtree_update(void)
  89 {
  90         variant_audio_update();
  91         variant_bluetooth_update();
  92         variant_touchscreen_update();
  93         variant_devtree_update();
  94 }
  95
  96 static void mainboard_init(void *chip_info)
  97 {
  98         int boardid;
  99
 100         mainboard_ec_init();
 101         boardid = board_id();
 102         printk(BIOS_INFO, "Board ID: %d\n", boardid);
 103
 104         mainboard_configure_gpios();
 105
 106         /* Update DUT configuration */
 107         mainboard_devtree_update();
 108 }
 109
 110 void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs,
 111                                         size_t *dxio_num,
 112                                         const fsp_ddi_descriptor **ddi_descs,
 113                                         size_t *ddi_num)
 114 {
 115         variant_get_dxio_ddi_descriptors(dxio_descs, dxio_num, ddi_descs, ddi_num);
 116 }
 117
 118 static void mainboard_write_blken(void)
 119 {
 120         acpigen_write_method(METHOD_BACKLIGHT_ENABLE, 0);
 121         acpigen_soc_clear_tx_gpio(GPIO_85);
 122         acpigen_pop_len();
 123 }
 124
 125 static void mainboard_write_blkdis(void)
 126 {
 127         acpigen_write_method(METHOD_BACKLIGHT_DISABLE, 0);
 128         acpigen_soc_set_tx_gpio(GPIO_85);
 129         acpigen_pop_len();
 130 }
 131
 132 static void mainboard_write_mini(void)
 133 {
 134         acpigen_write_method(METHOD_MAINBOARD_INI, 0);
 135         acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE);
 136         acpigen_pop_len();
 137 }
 138
 139 static void mainboard_write_mwak(void)
 140 {
 141         acpigen_write_method(METHOD_MAINBOARD_WAK, 0);
 142         acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE);
 143         acpigen_pop_len();
 144 }
 145
 146 static void mainboard_write_mpts(void)
 147 {
 148         acpigen_write_method(METHOD_MAINBOARD_PTS, 0);
 149         acpigen_emit_namestring(METHOD_BACKLIGHT_DISABLE);
 150         acpigen_pop_len();
 151 }
 152
 153 static void mainboard_fill_ssdt(const struct device *dev)
 154 {
 155         mainboard_write_blken();
 156         mainboard_write_blkdis();
 157         mainboard_write_mini();
 158         mainboard_write_mpts();
 159         mainboard_write_mwak();
 160 }
 161
 162 /*************************************************
 163  * Dedicated mainboard function
 164  *************************************************/
 165 static void mainboard_enable(struct device *dev)
 166 {
 167         dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 168 }
 169
 170 static void mainboard_final(void *chip_info)
 171 {
 172         finalize_gpios(acpi_get_sleep_type());
 173 }
 174
 175 struct chip_operations mainboard_ops = {
 176         .init = mainboard_init,
 177         .enable_dev = mainboard_enable,
 178         .final = mainboard_final,
 179 };
 180
 181 void __weak variant_devtree_update(void)
 182 {
 183 }
 184
 185 __weak const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 186 {
 187         /* Default weak implementation - No overrides. */
 188         *size = 0;
 189         return NULL;
 190 }