soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / soc / intel / pantherlake / p2sb.c
blob52b36903d6ce89b960c27ec430d02c81b0c7ce52
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci_def.h>
6 #include <intelblocks/p2sb.h>
7 #include <soc/iomap.h>
9 void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
11 uint32_t mask;
13 if (count != P2SB_EP_MASK_MAX_REG) {
14 printk(BIOS_ERR, "Unable to program EPMASK registers\n");
15 return;
18 /* Remove the host accessing right to PSF register range.
19 * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband
20 * access for PCI Root Bridge.
22 mask = BIT(29) | BIT(28) | BIT(27) | BIT(26);
24 ep_mask[P2SB_EP_MASK_5_REG] = mask;
27 * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband
28 * access for Broadcast and Multicast.
30 mask = BIT(31) | BIT(30);
32 ep_mask[P2SB_EP_MASK_7_REG] = mask;
35 static void p2sb2_read_resources(struct device *dev)
37 /* Add the fixed MMIO resource for P2SB#2 */
38 mmio_range(dev, PCI_BASE_ADDRESS_0, IOE_P2SB_BAR, IOE_P2SB_SIZE);
41 static void p2sb_read_resources(struct device *dev)
43 /* Add the fixed MMIO resource for P2SB#1 */
44 mmio_range(dev, PCI_BASE_ADDRESS_0, P2SB_BAR, P2SB_SIZE);
47 struct device_operations pcd_p2sb_2_ops = {
48 .read_resources = p2sb2_read_resources,
49 .set_resources = noop_set_resources,
50 .scan_bus = scan_static_bus,
53 struct device_operations pcd_p2sb_ops = {
54 .read_resources = p2sb_read_resources,
55 .set_resources = noop_set_resources,
56 .scan_bus = scan_static_bus,