src/soc/intel/xeon_sp/iio_ioapic.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <arch/ioapic.h>
   4 #include <device/pci_ids.h>
   5 #include <device/pci_ops.h>
   6 #include <intelblocks/acpi.h>
   7 #include <soc/util.h>
   8 #include <soc/pci_devs.h>
   9 #include <stdint.h>
  10
  11 static uintptr_t xeonsp_ioapic_bases[CONFIG_MAX_SOCKET * MAX_IIO_STACK + 1];
  12
  13 size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[])
  14 {
  15         struct device *dev = NULL;
  16         int index = 0;
  17
  18         *ioapic_bases = xeonsp_ioapic_bases;
  19
  20         /*
  21          * Stack 0 has non-PCH IOAPIC and PCH IOAPIC.
  22          * The IIO IOAPIC is placed at 0x1000 from the reported base.
  23          */
  24         xeonsp_ioapic_bases[index++] = IO_APIC_ADDR;
  25
  26         while ((dev = dev_find_class(PCI_CLASS_SYSTEM_PIC << 8, dev))) {
  27                 if (!is_pci_ioapic(dev))
  28                         continue;
  29
  30                 u16 abar = pci_read_config16(dev, APIC_ABAR);
  31                 if (!abar)
  32                         continue;
  33                 const u32 addr = IO_APIC_ADDR | ((abar & 0xfff) << 8);
  34
  35                 printk(BIOS_DEBUG, "%s: %s: IOAPIC Address: 0x%x\n",
  36                        __func__, dev_path(dev), addr);
  37                 xeonsp_ioapic_bases[index++] = addr;
  38         }
  39
  40         return index;
  41 }