src/soc/mediatek/mt8188/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
   2
   3 /*
   4  * This file is created based on MT8188 Functional Specification
   5  * Chapter number: 5.2
   6  */
   7
   8 #include <device/mmio.h>
   9 #include <gpio.h>
  10
  11 #define SPI_AP_GPIO_BASE        125
  12
  13 enum {
  14         SPI_AP_CLK_ROM = 0,
  15         SPI_AP_CS_ROM_L = 1,
  16         SPI_AP_DO_ROM_DI = 2,
  17         SPI_AP_DI_ROM_DO = 3,
  18 };
  19
  20 static const struct gpio_drv_info bootblock_gpio_driving_info[] = {
  21         [SPI_AP_CLK_ROM] = { 0x20, 24, 3, },
  22         [SPI_AP_CS_ROM_L] = { 0x20, 24, 3, },
  23         [SPI_AP_DO_ROM_DI] = { 0x20, 24, 3, },
  24         [SPI_AP_DI_ROM_DO] = { 0x20, 27, 3, },
  25 };
  26
  27 static const struct gpio_drv_info gpio_driving_info[] = {
  28         [0] = { 0x00, 24, 3, },
  29         [1] = { 0x00, 27, 3, },
  30         [2] = { 0x10, 0, 3, },
  31         [3] = { 0x10, 3, 3, },
  32         [4] = { 0x20, 9, 3, },
  33         [5] = { 0x20, 9, 3, },
  34         [6] = { 0x20, 9, 3, },
  35         [7] = { 0x10, 6, 3, },
  36         [8] = { 0x10, 9, 3, },
  37         [9] = { 0x10, 12, 3, },
  38         [10] = { 0x10, 15, 3, },
  39         [11] = { 0x20, 12, 3, },
  40         [12] = { 0x10, 24, 3, },
  41         [13] = { 0x10, 27, 3, },
  42         [14] = { 0x20, 0, 3, },
  43         [15] = { 0x20, 3, 3, },
  44         [16] = { 0x10, 15, 3, },
  45         [17] = { 0x10, 15, 3, },
  46         [18] = { 0x00, 27, 3, },
  47         [19] = { 0x00, 27, 3, },
  48         [20] = { 0x00, 27, 3, },
  49         [21] = { 0x00, 27, 3, },
  50         [22] = { 0x00, 0, 3, },
  51         [23] = { 0x00, 3, 3, },
  52         [24] = { 0x00, 6, 3, },
  53         [25] = { 0x20, 6, 3, },
  54         [26] = { 0x20, 6, 3, },
  55         [27] = { 0x20, 6, 3, },
  56         [28] = { 0x20, 9, 3, },
  57         [29] = { 0x20, 3, 3, },
  58         [30] = { 0x20, 6, 3, },
  59         [31] = { 0x20, 12, 3, },
  60         [32] = { 0x20, 12, 3, },
  61         [33] = { 0x20, 15, 3, },
  62         [34] = { 0x20, 15, 3, },
  63         [35] = { 0x20, 12, 3, },
  64         [36] = { 0x20, 15, 3, },
  65         [37] = { 0x10, 27, 3, },
  66         [38] = { 0x10, 18, 3, },
  67         [39] = { 0x10, 21, 3, },
  68         [40] = { 0x10, 24, 3, },
  69         [41] = { 0x20, 0, 3, },
  70         [42] = { 0x20, 18, 3, },
  71         [43] = { 0x20, 18, 3, },
  72         [44] = { 0x20, 18, 3, },
  73         [45] = { 0x20, 21, 3, },
  74         [46] = { 0x10, 15, 3, },
  75         [47] = { 0x20, 3, 3, },
  76         [48] = { 0x20, 3, 3, },
  77         [49] = { 0x20, 3, 3, },
  78         [50] = { 0x00, 6, 3, },
  79         [51] = { 0x00, 3, 3, },
  80         [52] = { 0x00, 0, 3, },
  81         [53] = { 0x00, 9, 3, },
  82         [54] = { 0x00, 12, 3, },
  83         [55] = { 0x20, 27, 3, },
  84         [56] = { 0x30, 6, 3, },
  85         [57] = { 0x30, 9, 3, },
  86         [58] = { 0x30, 15, 3, },
  87         [59] = { 0x30, 0, 3, },
  88         [60] = { 0x30, 9, 3, },
  89         [61] = { 0x30, 3, 3, },
  90         [62] = { 0x30, 12, 3, },
  91         [63] = { 0x30, 12, 3, },
  92         [64] = { 0x30, 18, 3, },
  93         [65] = { 0x10, 0, 3, },
  94         [66] = { 0x10, 6, 3, },
  95         [67] = { 0x10, 3, 3, },
  96         [68] = { 0x10, 9, 3, },
  97         [69] = { 0x30, 18, 3, },
  98         [70] = { 0x30, 15, 3, },
  99         [71] = { 0x40, 0, 3, },
 100         [72] = { 0x30, 27, 3, },
 101         [73] = { 0x30, 21, 3, },
 102         [74] = { 0x30, 24, 3, },
 103         [75] = { 0x40, 6, 3, },
 104         [76] = { 0x40, 3, 3, },
 105         [77] = { 0x40, 12, 3, },
 106         [78] = { 0x40, 9, 3, },
 107         [79] = { 0x10, 15, 3, },
 108         [80] = { 0x10, 12, 3, },
 109         [81] = { 0x10, 21, 3, },
 110         [82] = { 0x10, 18, 3, },
 111         [83] = { 0x30, 0, 3, },
 112         [84] = { 0x20, 27, 3, },
 113         [85] = { 0x30, 0, 3, },
 114         [86] = { 0x20, 6, 3, },
 115         [87] = { 0x20, 6, 3, },
 116         [88] = { 0x20, 6, 3, },
 117         [89] = { 0x20, 6, 3, },
 118         [90] = { 0x30, 0, 3, },
 119         [91] = { 0x30, 0, 3, },
 120         [92] = { 0x20, 9, 3, },
 121         [93] = { 0x20, 9, 3, },
 122         [94] = { 0x20, 9, 3, },
 123         [95] = { 0x20, 9, 3, },
 124         [96] = { 0x20, 21, 3, },
 125         [97] = { 0x20, 21, 3, },
 126         [98] = { 0x20, 24, 3, },
 127         [99] = { 0x20, 21, 3, },
 128         [100] = { 0x30, 6, 3, },
 129         [101] = { 0x00, 0, 3, },
 130         [102] = { 0x00, 15, 3, },
 131         [103] = { 0x00, 9, 3, },
 132         [104] = { 0x00, 12, 3, },
 133         [105] = { 0x00, 3, 3, },
 134         [106] = { 0x00, 6, 3, },
 135         [107] = { 0x20, 6, 3, },
 136         [108] = { 0x20, 6, 3, },
 137         [109] = { 0x20, 6, 3, },
 138         [110] = { 0x20, 6, 3, },
 139         [111] = { 0x20, 15, 3, },
 140         [112] = { 0x20, 15, 3, },
 141         [113] = { 0x20, 15, 3, },
 142         [114] = { 0x20, 12, 3, },
 143         [115] = { 0x20, 12, 3, },
 144         [116] = { 0x20, 12, 3, },
 145         [117] = { 0x20, 12, 3, },
 146         [118] = { 0x20, 12, 3, },
 147         [119] = { 0x20, 15, 3, },
 148         [120] = { 0x20, 18, 3, },
 149         [121] = { 0x10, 3, 3, },
 150         [122] = { 0x10, 12, 3, },
 151         [123] = { 0x10, 9, 3, },
 152         [124] = { 0x10, 6, 3, },
 153         [125] = { 0x20, 24, 3, },
 154         [126] = { 0x20, 24, 3, },
 155         [127] = { 0x20, 24, 3, },
 156         [128] = { 0x20, 27, 3, },
 157         [129] = { 0x20, 27, 3, },
 158         [130] = { 0x20, 27, 3, },
 159         [131] = { 0x00, 0, 3, },
 160         [132] = { 0x00, 15, 3, },
 161         [133] = { 0x00, 18, 3, },
 162         [134] = { 0x00, 21, 3, },
 163         [135] = { 0x20, 15, 3, },
 164         [136] = { 0x20, 18, 3, },
 165         [137] = { 0x20, 18, 3, },
 166         [138] = { 0x20, 18, 3, },
 167         [139] = { 0x20, 18, 3, },
 168         [140] = { 0x20, 21, 3, },
 169         [141] = { 0x20, 21, 3, },
 170         [142] = { 0x20, 21, 3, },
 171         [143] = { 0x00, 3, 3, },
 172         [144] = { 0x00, 6, 3, },
 173         [145] = { 0x00, 9, 3, },
 174         [146] = { 0x00, 12, 3, },
 175         [147] = { 0x20, 21, 3, },
 176         [148] = { 0x20, 24, 3, },
 177         [149] = { 0x20, 24, 3, },
 178         [150] = { 0x20, 24, 3, },
 179         [151] = { 0x10, 15, 3, },
 180         [152] = { 0x10, 12, 3, },
 181         [153] = { 0x10, 9, 3, },
 182         [154] = { 0x10, 6, 3, },
 183         [155] = { 0x10, 21, 3, },
 184         [156] = { 0x00, 21, 3, },
 185         [157] = { 0x00, 18, 3, },
 186         [158] = { 0x10, 3, 3, },
 187         [159] = { 0x10, 0, 3, },
 188         [160] = { 0x00, 27, 3, },
 189         [161] = { 0x00, 24, 3, },
 190         [162] = { 0x10, 18, 3, },
 191         [163] = { 0x00, 12, 3, },
 192         [164] = { 0x00, 9, 3, },
 193         [165] = { 0x00, 15, 3, },
 194         [166] = { 0x00, 18, 3, },
 195         [167] = { 0x00, 21, 3, },
 196         [168] = { 0x00, 24, 3, },
 197         [169] = { 0x00, 18, 3, },
 198         [170] = { 0x00, 15, 3, },
 199         [171] = { 0x00, 21, 3, },
 200         [172] = { 0x00, 24, 3, },
 201         [173] = { 0x00, 27, 3, },
 202         [174] = { 0x10, 0, 3, },
 203         [175] = { 0x30, 3, 3, },
 204         [176] = { 0x30, 3, 3, },
 205 };
 206
 207 _Static_assert(ARRAY_SIZE(gpio_driving_info) == GPIO_NUM,
 208                "gpio_driving_info array size not match");
 209
 210 /* Unimplemented GPIOs are intentionally omitted here with width=0 */
 211 static const struct gpio_drv_info gpio_driving_adv_info[] = {
 212         [53] = { 0x20, 0, 3, },
 213         [54] = { 0x20, 3, 3, },
 214         [55] = { 0x60, 0, 3, },
 215         [56] = { 0x60, 9, 3, },
 216         [57] = { 0x50, 0, 3, },
 217         [58] = { 0x50, 6, 3, },
 218         [59] = { 0x60, 3, 3, },
 219         [60] = { 0x60, 12, 3, },
 220         [61] = { 0x60, 6, 3, },
 221         [62] = { 0x60, 15, 3, },
 222         [63] = { 0x50, 3, 3, },
 223         [64] = { 0x50, 9, 3, },
 224         [65] = { 0x30, 0, 3, },
 225         [66] = { 0x30, 6, 3, },
 226         [67] = { 0x30, 3, 3, },
 227         [68] = { 0x30, 9, 3, },
 228         [175] = { 0x50, 12, 3, },
 229         [176] = { 0x50, 15, 3, },
 230 };
 231
 232 void *gpio_find_reg_addr(gpio_t gpio)
 233 {
 234         void *reg_addr;
 235         switch (gpio.base & 0x0f) {
 236         case 1:
 237                 reg_addr = (void *)IOCFG_RM_BASE;
 238                 break;
 239         case 2:
 240                 reg_addr = (void *)IOCFG_LT_BASE;
 241                 break;
 242         case 3:
 243                 reg_addr = (void *)IOCFG_LM_BASE;
 244                 break;
 245         case 4:
 246                 reg_addr = (void *)IOCFG_RT_BASE;
 247                 break;
 248         default:
 249                 reg_addr = NULL;
 250                 break;
 251         }
 252
 253         return reg_addr;
 254 }
 255
 256 const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id)
 257 {
 258         if (ENV_BOOTBLOCK) {
 259                 uint32_t id = raw_id - SPI_AP_GPIO_BASE;
 260
 261                 if (id >= ARRAY_SIZE(bootblock_gpio_driving_info))
 262                         return NULL;
 263                 return &bootblock_gpio_driving_info[id];
 264         } else {
 265                 if (raw_id >= ARRAY_SIZE(gpio_driving_info))
 266                         return NULL;
 267                 return &gpio_driving_info[raw_id];
 268         }
 269 }
 270
 271 const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id)
 272 {
 273         if (ENV_BOOTBLOCK) {
 274                 return NULL;
 275         } else {
 276                 if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info))
 277                         return NULL;
 278                 return &gpio_driving_adv_info[raw_id];
 279         }
 280 }