src/soc/mediatek/mt8188/spm.c

   1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
   2
   3 #include <soc/mcu_common.h>
   4 #include <soc/pll.h>
   5 #include <soc/spm.h>
   6
   7 static struct pwr_ctrl spm_init_ctrl = {
   8         /* For SPM, this flag is not auto-gen. */
   9         .pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS |
  10                      SPM_FLAG_DISABLE_VCORE_DFS |
  11                      SPM_FLAG_RUN_COMMON_SCENARIO,
  12         /* SPM_AP_STANDBY_CON */
  13         /* [0] */
  14         .reg_wfi_op = 0,
  15         /* [1] */
  16         .reg_wfi_type = 0,
  17         /* [2] */
  18         .reg_mp0_cputop_idle_mask = 0,
  19         /* [3] */
  20         .reg_mp1_cputop_idle_mask = 0,
  21         /* [4] */
  22         .reg_mcusys_idle_mask = 0,
  23         /* [25] */
  24         .reg_md_apsrc_1_sel = 0,
  25         /* [26] */
  26         .reg_md_apsrc_0_sel = 0,
  27         /* [29] */
  28         .reg_conn_apsrc_sel = 0,
  29
  30         /* SPM_SRC_REQ */
  31         /* [0] */
  32         .reg_spm_apsrc_req = 0,
  33         /* [1] */
  34         .reg_spm_f26m_req = 0,
  35         /* [3] */
  36         .reg_spm_infra_req = 0,
  37         /* [4] */
  38         .reg_spm_vrf18_req = 0,
  39         /* [7] */
  40         .reg_spm_ddr_en_req = 0,
  41         /* [8] */
  42         .reg_spm_dvfs_req = 0,
  43         /* [9] */
  44         .reg_spm_sw_mailbox_req = 0,
  45         /* [10] */
  46         .reg_spm_sspm_mailbox_req = 0,
  47         /* [11] */
  48         .reg_spm_adsp_mailbox_req = 0,
  49         /* [12] */
  50         .reg_spm_scp_mailbox_req = 0,
  51
  52
  53         /* SPM_SRC_MASK */
  54         /* [0] */
  55         .reg_sspm_srcclkena_0_mask_b = 1,
  56         /* [1] */
  57         .reg_sspm_infra_req_0_mask_b = 1,
  58         /* [2] */
  59         .reg_sspm_apsrc_req_0_mask_b = 1,
  60         /* [3] */
  61         .reg_sspm_vrf18_req_0_mask_b = 1,
  62         /* [4] */
  63         .reg_sspm_ddr_en_0_mask_b = 1,
  64         /* [5] */
  65         .reg_scp_srcclkena_mask_b = 1,
  66         /* [6] */
  67         .reg_scp_infra_req_mask_b = 1,
  68         /* [7] */
  69         .reg_scp_apsrc_req_mask_b = 1,
  70         /* [8] */
  71         .reg_scp_vrf18_req_mask_b = 1,
  72         /* [9] */
  73         .reg_scp_ddr_en_mask_b = 1,
  74         /* [10] */
  75         .reg_audio_dsp_srcclkena_mask_b = 1,
  76         /* [11] */
  77         .reg_audio_dsp_infra_req_mask_b = 1,
  78         /* [12] */
  79         .reg_audio_dsp_apsrc_req_mask_b = 1,
  80         /* [13] */
  81         .reg_audio_dsp_vrf18_req_mask_b = 1,
  82         /* [14] */
  83         .reg_audio_dsp_ddr_en_mask_b = 1,
  84         /* [15] */
  85         .reg_apu_srcclkena_mask_b = 1,
  86         /* [16] */
  87         .reg_apu_infra_req_mask_b = 1,
  88         /* [17] */
  89         .reg_apu_apsrc_req_mask_b = 1,
  90         /* [18] */
  91         .reg_apu_vrf18_req_mask_b = 1,
  92         /* [19] */
  93         .reg_apu_ddr_en_mask_b = 1,
  94         /* [20] */
  95         .reg_cpueb_srcclkena_mask_b = 1,
  96         /* [21] */
  97         .reg_cpueb_infra_req_mask_b = 1,
  98         /* [22] */
  99         .reg_cpueb_apsrc_req_mask_b = 1,
 100         /* [23] */
 101         .reg_cpueb_vrf18_req_mask_b = 1,
 102         /* [24] */
 103         .reg_cpueb_ddr_en_mask_b = 1,
 104         /* [25] */
 105         .reg_bak_psri_srcclkena_mask_b = 0,
 106         /* [26] */
 107         .reg_bak_psri_infra_req_mask_b = 0,
 108         /* [27] */
 109         .reg_bak_psri_apsrc_req_mask_b = 0,
 110         /* [28] */
 111         .reg_bak_psri_vrf18_req_mask_b = 0,
 112         /* [29] */
 113         .reg_bak_psri_ddr_en_mask_b = 0,
 114         /* [30] */
 115         .reg_cam_ddren_req_mask_b = 1,
 116         /* [31] */
 117         .reg_img_ddren_req_mask_b = 1,
 118
 119         /* SPM_SRC2_MASK */
 120         /* [0] */
 121         .reg_msdc0_srcclkena_mask_b = 1,
 122         /* [1] */
 123         .reg_msdc0_infra_req_mask_b = 1,
 124         /* [2] */
 125         .reg_msdc0_apsrc_req_mask_b = 1,
 126         /* [3] */
 127         .reg_msdc0_vrf18_req_mask_b = 1,
 128         /* [4] */
 129         .reg_msdc0_ddr_en_mask_b = 1,
 130         /* [5] */
 131         .reg_msdc1_srcclkena_mask_b = 1,
 132         /* [6] */
 133         .reg_msdc1_infra_req_mask_b = 1,
 134         /* [7] */
 135         .reg_msdc1_apsrc_req_mask_b = 1,
 136         /* [8] */
 137         .reg_msdc1_vrf18_req_mask_b = 1,
 138         /* [9] */
 139         .reg_msdc1_ddr_en_mask_b = 1,
 140         /* [10] */
 141         .reg_msdc2_srcclkena_mask_b = 1,
 142         /* [11] */
 143         .reg_msdc2_infra_req_mask_b = 1,
 144         /* [12] */
 145         .reg_msdc2_apsrc_req_mask_b = 1,
 146         /* [13] */
 147         .reg_msdc2_vrf18_req_mask_b = 1,
 148         /* [14] */
 149         .reg_msdc2_ddr_en_mask_b = 1,
 150         /* [15] */
 151         .reg_ufs_srcclkena_mask_b = 1,
 152         /* [16] */
 153         .reg_ufs_infra_req_mask_b = 1,
 154         /* [17] */
 155         .reg_ufs_apsrc_req_mask_b = 1,
 156         /* [18] */
 157         .reg_ufs_vrf18_req_mask_b = 1,
 158         /* [19] */
 159         .reg_ufs_ddr_en_mask_b = 1,
 160         /* [20] */
 161         .reg_usb_srcclkena_mask_b = 1,
 162         /* [21] */
 163         .reg_usb_infra_req_mask_b = 1,
 164         /* [22] */
 165         .reg_usb_apsrc_req_mask_b = 1,
 166         /* [23] */
 167         .reg_usb_vrf18_req_mask_b = 1,
 168         /* [24] */
 169         .reg_usb_ddr_en_mask_b = 1,
 170         /* [25] */
 171         .reg_pextp_p0_srcclkena_mask_b = 1,
 172         /* [26] */
 173         .reg_pextp_p0_infra_req_mask_b = 1,
 174         /* [27] */
 175         .reg_pextp_p0_apsrc_req_mask_b = 1,
 176         /* [28] */
 177         .reg_pextp_p0_vrf18_req_mask_b = 1,
 178         /* [29] */
 179         .reg_pextp_p0_ddr_en_mask_b = 1,
 180
 181         /* SPM_SRC3_MASK */
 182         /* [0] */
 183         .reg_pextp_p1_srcclkena_mask_b = 1,
 184         /* [1] */
 185         .reg_pextp_p1_infra_req_mask_b = 1,
 186         /* [2] */
 187         .reg_pextp_p1_apsrc_req_mask_b = 1,
 188         /* [3] */
 189         .reg_pextp_p1_vrf18_req_mask_b = 1,
 190         /* [4] */
 191         .reg_pextp_p1_ddr_en_mask_b = 1,
 192         /* [5] */
 193         .reg_gce0_infra_req_mask_b = 1,
 194         /* [6] */
 195         .reg_gce0_apsrc_req_mask_b = 1,
 196         /* [7] */
 197         .reg_gce0_vrf18_req_mask_b = 1,
 198         /* [8] */
 199         .reg_gce0_ddr_en_mask_b = 1,
 200         /* [9] */
 201         .reg_gce1_infra_req_mask_b = 1,
 202         /* [10] */
 203         .reg_gce1_apsrc_req_mask_b = 1,
 204         /* [11] */
 205         .reg_gce1_vrf18_req_mask_b = 1,
 206         /* [12] */
 207         .reg_gce1_ddr_en_mask_b = 1,
 208         /* [13] */
 209         .reg_spm_srcclkena_reserved_mask_b = 1,
 210         /* [14] */
 211         .reg_spm_infra_req_reserved_mask_b = 1,
 212         /* [15] */
 213         .reg_spm_apsrc_req_reserved_mask_b = 1,
 214         /* [16] */
 215         .reg_spm_vrf18_req_reserved_mask_b = 1,
 216         /* [17] */
 217         .reg_spm_ddr_en_reserved_mask_b = 1,
 218         /* [18] */
 219         .reg_disp0_apsrc_req_mask_b = 1,
 220         /* [19] */
 221         .reg_disp0_ddr_en_mask_b = 1,
 222         /* [20] */
 223         .reg_disp1_apsrc_req_mask_b = 1,
 224         /* [21] */
 225         .reg_disp1_ddr_en_mask_b = 1,
 226         /* [22] */
 227         .reg_disp2_apsrc_req_mask_b = 1,
 228         /* [23] */
 229         .reg_disp2_ddr_en_mask_b = 1,
 230         /* [24] */
 231         .reg_disp3_apsrc_req_mask_b = 1,
 232         /* [25] */
 233         .reg_disp3_ddr_en_mask_b = 1,
 234         /* [26] */
 235         .reg_infrasys_apsrc_req_mask_b = 0,
 236         /* [27] */
 237         .reg_infrasys_ddr_en_mask_b = 1,
 238
 239         /* [28] */
 240         .reg_cg_check_srcclkena_mask_b = 1,
 241         /* [29] */
 242         .reg_cg_check_apsrc_req_mask_b = 1,
 243         /* [30] */
 244         .reg_cg_check_vrf18_req_mask_b = 1,
 245         /* [31] */
 246         .reg_cg_check_ddr_en_mask_b = 1,
 247
 248         /* SPM_SRC4_MASK */
 249         /* [8:0] */
 250         .reg_mcusys_merge_apsrc_req_mask_b = 0,
 251         /* [17:9] */
 252         .reg_mcusys_merge_ddr_en_mask_b = 0,
 253         /* [19:18] */
 254         .reg_dramc_md32_infra_req_mask_b = 3,
 255         /* [21:20] */
 256         .reg_dramc_md32_vrf18_req_mask_b = 3,
 257         /* [23:22] */
 258         .reg_dramc_md32_ddr_en_mask_b = 0,
 259         /* [24] */
 260         .reg_dvfsrc_event_trigger_mask_b = 1,
 261
 262         /* SPM_WAKEUP_EVENT_MASK2 */
 263         /* [3:0] */
 264         .reg_sc_sw2spm_wakeup_mask_b = 0,
 265         /* [4] */
 266         .reg_sc_adsp2spm_wakeup_mask_b = 0,
 267         /* [8:5] */
 268         .reg_sc_sspm2spm_wakeup_mask_b = 0,
 269         /* [9] */
 270         .reg_sc_scp2spm_wakeup_mask_b = 0,
 271         /* [10] */
 272         .reg_csyspwrup_ack_mask = 0,
 273         /* [11] */
 274         .reg_csyspwrup_req_mask = 1,
 275
 276         /* SPM_WAKEUP_EVENT_MASK */
 277         /* [31:0] */
 278         .reg_wakeup_event_mask = 0xC1382213,
 279
 280         /* SPM_WAKEUP_EVENT_EXT_MASK */
 281         /* [31:0] */
 282         .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
 283 };
 284
 285 static void spm_hw_s1_state_monitor_pause(void)
 286 {
 287         SET32_BITFIELDS(&mtk_spm->spm_ack_chk_con_3,
 288                         SPM_ACK_CHK_3_CON_HW_MODE_TRIG, 1,
 289                         SPM_ACK_CHK_3_CON_CLR_ALL, 1,
 290                         SPM_ACK_CHK_3_CON_EN_0, 0,
 291                         SPM_ACK_CHK_3_CON_EN_1, 0);
 292 }
 293
 294 void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
 295 {
 296         /* SPM_AP_STANDBY_CON */
 297         write32(&mtk_spm->spm_ap_standby_con,
 298                 ((pwrctrl->reg_wfi_op & 0x1) << 0) |
 299                 ((pwrctrl->reg_wfi_type & 0x1) << 1) |
 300                 ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
 301                 ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
 302                 ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
 303                 ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
 304                 ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
 305                 ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
 306
 307         /* SPM_SRC_REQ */
 308         write32(&mtk_spm->spm_src_req,
 309                 ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
 310                 ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
 311                 ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
 312                 ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
 313                 ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
 314                 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
 315                 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
 316                 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
 317                 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
 318                 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
 319
 320         /* SPM_SRC_MASK */
 321         write32(&mtk_spm->spm_src_mask,
 322                 ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
 323                 ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
 324                 ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
 325                 ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
 326                 ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
 327                 ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
 328                 ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
 329                 ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
 330                 ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
 331                 ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
 332                 ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
 333                 ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
 334                 ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
 335                 ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
 336                 ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
 337                 ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
 338                 ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
 339                 ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
 340                 ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
 341                 ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
 342                 ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
 343                 ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
 344                 ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
 345                 ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
 346                 ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
 347                 ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
 348                 ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
 349                 ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
 350                 ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
 351                 ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29) |
 352                 ((pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 30) |
 353                 ((pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 31));
 354
 355         /* SPM_SRC2_MASK */
 356         write32(&mtk_spm->spm_src2_mask,
 357                 ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
 358                 ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
 359                 ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
 360                 ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
 361                 ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
 362                 ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
 363                 ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
 364                 ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
 365                 ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
 366                 ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
 367                 ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
 368                 ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
 369                 ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
 370                 ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
 371                 ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
 372                 ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
 373                 ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
 374                 ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
 375                 ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
 376                 ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
 377                 ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
 378                 ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
 379                 ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
 380                 ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
 381                 ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
 382                 ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
 383                 ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
 384                 ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
 385                 ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
 386                 ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
 387
 388         /* SPM_SRC3_MASK */
 389         write32(&mtk_spm->spm_src3_mask,
 390                 ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
 391                 ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
 392                 ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
 393                 ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
 394                 ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
 395                 ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
 396                 ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
 397                 ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
 398                 ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
 399                 ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
 400                 ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
 401                 ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
 402                 ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
 403                 ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
 404                 ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
 405                 ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
 406                 ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
 407                 ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
 408                 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
 409                 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
 410                 ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
 411                 ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
 412                 ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
 413                 ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
 414                 ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
 415                 ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
 416                 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
 417                 ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
 418
 419         /* SPM_SRC4_MASK */
 420         write32(&mtk_spm->spm_src4_mask,
 421                 ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
 422                 ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
 423                 ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 18) |
 424                 ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 20) |
 425                 ((pwrctrl->reg_dramc_md32_ddr_en_mask_b & 0x3) << 22) |
 426                 ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 24));
 427
 428         /* SPM_WAKEUP_EVENT_MASK */
 429         write32(&mtk_spm->spm_wakeup_event_mask,
 430                 ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
 431
 432         /* SPM_WAKEUP_EVENT_EXT_MASK */
 433         write32(&mtk_spm->spm_wakeup_event_ext_mask,
 434                 ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
 435 }
 436
 437 void spm_register_init(void)
 438 {
 439         /* set clock path for SPM */
 440         setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x7ff);
 441         /* enable register control */
 442         write32(&mtk_spm->poweron_config_set, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
 443         /* init power control register, dram will set this register */
 444         write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF);
 445         write32(&mtk_spm->pcm_pwr_io_en, 0);
 446         /* reset PCM */
 447         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB |
 448                                     PCM_SW_RESET_LSB);
 449         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
 450         write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
 451                                     REG_SPM_SRAM_ISOINT_B_LSB |
 452                                     RG_AHBMIF_APBEN_LSB |
 453                                     REG_MD32_APB_INTERNAL_EN_LSB);
 454         /* clean wakeup event raw status */
 455         write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF);
 456         /* clean ISR status */
 457         write32(&mtk_spm->spm_irq_mask, ISRM_ALL);
 458         write32(&mtk_spm->spm_irq_sta, ISRC_ALL);
 459         write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL);
 460         /* init r7 with POWER_ON_VAL1 */
 461         write32(&mtk_spm->pcm_reg_data_ini, read32(&mtk_spm->spm_power_on_val1));
 462         write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
 463         write32(&mtk_spm->pcm_pwr_io_en, 0);
 464         /* DDR EN de-bounce length to 5us */
 465         write32(&mtk_spm->ddren_dbc_con, 0x154 | REG_ALL_DDR_EN_DBC_EN_LSB);
 466         /* configure ARMPLL Control Mode for MCDI */
 467         write32(&mtk_spm->armpll_clk_sel, 0x3FF);
 468         /* init for SPM Resource ACK */
 469         write32(&mtk_spm->spm_resource_ack_con0, 0xFFFFFFFF);
 470         write32(&mtk_spm->spm_resource_ack_con1, 0xFFFFFFFF);
 471         write32(&mtk_spm->spm_resource_ack_con2, 0xFFFFFFFF);
 472         write32(&mtk_spm->spm_resource_ack_con3, 0xFFFFFFFF);
 473         /* init VCORE DVFS Status */
 474         write32(&mtk_spm->spm_dvfs_level, 0x00000001);
 475         write32(&mtk_spm->spm_dvs_dfs_level, 0x00010001);
 476         SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc,
 477                         SPM_DVFS_FORCE_ENABLE_LSB, 0,
 478                         SPM_DVFSRC_ENABLE_LSB, 1);
 479         write32(&mtk_spm->spm_dvfs_level, 0x00000001);
 480         write32(&mtk_spm->spm_dvs_dfs_level, 0x00010001);
 481         /* HW S1 state monitor */
 482         write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1);
 483         write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT);
 484         spm_hw_s1_state_monitor_pause();
 485 }
 486
 487 void spm_reset_and_init_pcm(void)
 488 {
 489         uint32_t val;
 490         bool first_load_fw = true;
 491
 492         /* check the SPM FW is run or not */
 493         if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) &
 494             MD32PCM_CFGREG_SW_RSTN_RUN)
 495                 first_load_fw = false;
 496
 497         if (!first_load_fw) {
 498                 /* SPM code swapping */
 499                 spm_code_swapping();
 500                 /* backup PCM r0 -> SPM_POWER_ON_VAL0 before `reset PCM` */
 501                 write32(&mtk_spm->spm_power_on_val0,
 502                         read32(&mtk_spm->pcm_reg0_data));
 503         }
 504
 505         /* disable r0 and r7 to control power */
 506         write32(&mtk_spm->pcm_pwr_io_en, 0);
 507
 508         /* disable pcm timer after leaving FW */
 509         clrsetbits32(&mtk_spm->pcm_con1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
 510
 511         /* reset PCM */
 512         write32(&mtk_spm->pcm_con0,
 513                 SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
 514         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
 515
 516         /* clear SPM EVENT count */
 517         setbits32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
 518         clrsetbits32(&mtk_spm->pcm_con1, SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
 519
 520         /* init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */
 521         val = read32(&mtk_spm->pcm_con1) & RG_PCM_WDT_WAKE_LSB;
 522         write32(&mtk_spm->pcm_con1, val | SPM_REGWR_CFG_KEY |
 523                                     REG_EVENT_LOCK_EN_LSB |
 524                                     REG_SPM_SRAM_ISOINT_B_LSB |
 525                                     RG_AHBMIF_APBEN_LSB |
 526                                     REG_MD32_APB_INTERNAL_EN_LSB);
 527 }
 528
 529 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
 530 {
 531         uint32_t val, mask;
 532
 533         /* toggle event counter clear */
 534         setbits32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
 535         /* toggle for reset SYS TIMER start point */
 536         SET32_BITFIELDS(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB, 1);
 537
 538         if (pwrctrl->timer_val_cust == 0)
 539                 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
 540         else
 541                 val = pwrctrl->timer_val_cust;
 542
 543         write32(&mtk_spm->pcm_timer_val, val);
 544         setbits32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
 545
 546         /* unmask AP wakeup source */
 547         if (pwrctrl->wake_src_cust == 0)
 548                 mask = pwrctrl->wake_src;
 549         else
 550                 mask = pwrctrl->wake_src_cust;
 551
 552         write32(&mtk_spm->spm_wakeup_event_mask, ~mask);
 553
 554         /* unmask SPM ISR (keep TWAM setting) */
 555         setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX);
 556         /* toggle event counter clear */
 557         clrsetbits32(&mtk_spm->pcm_con1, SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
 558         /* toggle for reset SYS TIMER start point */
 559         SET32_BITFIELDS(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB, 0);
 560 }
 561
 562 const struct pwr_ctrl *get_pwr_ctrl(void)
 563 {
 564         return &spm_init_ctrl;
 565 }