src/soc/qualcomm/ipq40xx/qup.c

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 #include <device/mmio.h>
   4 #include <console/console.h>
   5 #include <delay.h>
   6 #include <timer.h>
   7 #include <soc/iomap.h>
   8 #include <soc/qup.h>
   9
  10 #define TIMEOUT_CNT     100
  11
  12 #define QUP_ADDR(id, reg)       (blsp_qup_base(id) + (reg))
  13
  14 #define QUP_DEBUG       0
  15
  16 #define QUPDBG          BIOS_ERR, "\t-> "
  17
  18 #if QUP_DEBUG
  19 #define qup_write32(a, v) do {                          \
  20         write32(a, v);                                  \
  21         printk(QUPDBG "%s(%d): write32(%p, 0x%x)\n",    \
  22                         __func__, __LINE__, a, v);      \
  23 } while (0)
  24 #else
  25 #define qup_write32     write32
  26 #endif
  27
  28 static qup_return_t qup_i2c_master_status(blsp_qup_id_t id)
  29 {
  30         uint32_t reg_val = read32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS));
  31
  32         if (read32(QUP_ADDR(id, QUP_ERROR_FLAGS)))
  33                 return QUP_ERR_XFER_FAIL;
  34
  35 #if QUP_DEBUG
  36         printk(QUPDBG "%s: 0x%x\n", __func__, reg_val);
  37 #endif
  38
  39         if (reg_val & QUP_I2C_INVALID_READ_ADDR)
  40                 return QUP_ERR_I2C_INVALID_SLAVE_ADDR;
  41         if (reg_val & QUP_I2C_FAILED_MASK)
  42                 return QUP_ERR_I2C_FAILED;
  43         if (reg_val & QUP_I2C_ARB_LOST)
  44                 return QUP_ERR_I2C_ARB_LOST;
  45         if (reg_val & QUP_I2C_BUS_ERROR)
  46                 return QUP_ERR_I2C_BUS_ERROR;
  47         if (reg_val & QUP_I2C_INVALID_WRITE)
  48                 return QUP_ERR_I2C_INVALID_WRITE;
  49         if (reg_val & QUP_I2C_PACKET_NACK)
  50                 return QUP_ERR_I2C_NACK;
  51         if (reg_val & QUP_I2C_INVALID_TAG)
  52                 return QUP_ERR_I2C_INVALID_TAG;
  53
  54         return QUP_SUCCESS;
  55 }
  56
  57 static int check_bit_state(uint32_t *reg, int wait_for)
  58 {
  59         unsigned int count = TIMEOUT_CNT;
  60
  61         while ((read32(reg) & (QUP_STATE_VALID_MASK | QUP_STATE_MASK)) !=
  62                         (QUP_STATE_VALID | wait_for)) {
  63                 if (count == 0)
  64                         return QUP_ERR_TIMEOUT;
  65                 count--;
  66         }
  67
  68         return QUP_SUCCESS;
  69 }
  70
  71 /*
  72  * Check whether GSBIn_QUP State is valid
  73  */
  74 static qup_return_t qup_wait_for_state(blsp_qup_id_t id, unsigned int wait_for)
  75 {
  76         return check_bit_state(QUP_ADDR(id, QUP_STATE), wait_for);
  77 }
  78
  79 qup_return_t qup_reset_i2c_master_status(blsp_qup_id_t id)
  80 {
  81         /*
  82          * The I2C_STATUS is a status register.
  83          * Writing any value clears the status bits.
  84          */
  85         qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS), 0);
  86         return QUP_SUCCESS;
  87 }
  88
  89 static qup_return_t qup_reset_master_status(blsp_qup_id_t id)
  90 {
  91         qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS), 0x3C);
  92         qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS_EN), 0x3C);
  93         qup_reset_i2c_master_status(id);
  94         return QUP_SUCCESS;
  95 }
  96
  97 static qup_return_t qup_fifo_wait_for(blsp_qup_id_t id, uint32_t status,
  98                                       struct stopwatch *timeout)
  99 {
 100         qup_return_t ret = QUP_ERR_UNDEFINED;
 101
 102         while (!(read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status)) {
 103                 ret = qup_i2c_master_status(id);
 104                 if (ret)
 105                         return ret;
 106                 if (stopwatch_expired(timeout))
 107                         return QUP_ERR_TIMEOUT;
 108         }
 109
 110         return QUP_SUCCESS;
 111 }
 112
 113 static qup_return_t qup_fifo_wait_while(blsp_qup_id_t id, uint32_t status,
 114                                         struct stopwatch *timeout)
 115 {
 116         qup_return_t ret = QUP_ERR_UNDEFINED;
 117
 118         while (read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status) {
 119                 ret = qup_i2c_master_status(id);
 120                 if (ret)
 121                         return ret;
 122                 if (stopwatch_expired(timeout))
 123                         return QUP_ERR_TIMEOUT;
 124         }
 125
 126         return QUP_SUCCESS;
 127 }
 128
 129 static inline uint32_t qup_i2c_create_output_tag(int stop, u8 data)
 130 {
 131         uint32_t tag;
 132
 133         if (stop)
 134                 tag = QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data);
 135         else
 136                 tag = QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data);
 137
 138         return tag;
 139 }
 140
 141 static inline qup_return_t qup_i2c_write_fifo_flush(blsp_qup_id_t id,
 142                                                     struct stopwatch *timeout)
 143 {
 144         qup_return_t ret = QUP_ERR_UNDEFINED;
 145
 146         qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), OUTPUT_SERVICE_FLAG);
 147
 148         mdelay(4);      /* TPM seems to need this */
 149
 150         ret = qup_fifo_wait_while(id, OUTPUT_FIFO_NOT_EMPTY, timeout);
 151         if (ret)
 152                 return ret;
 153
 154         ret = qup_i2c_master_status(id);
 155
 156         if (ret)
 157                 printk(BIOS_DEBUG, "%s: error\n", __func__);
 158
 159         return ret;
 160 }
 161
 162 static qup_return_t qup_i2c_write_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj,
 163                                        uint8_t stop_seq)
 164 {
 165         qup_return_t ret = QUP_ERR_UNDEFINED;
 166         uint8_t addr = p_tx_obj->p.iic.addr;
 167         uint8_t *data_ptr = p_tx_obj->p.iic.data;
 168         unsigned int data_len = p_tx_obj->p.iic.data_len;
 169         unsigned int idx = 0;
 170         uint32_t tag, *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO);
 171         struct stopwatch timeout;
 172
 173         qup_reset_master_status(id);
 174
 175         qup_write32(QUP_ADDR(id, QUP_MX_OUTPUT_COUNT), data_len + 1);
 176
 177         qup_set_state(id, QUP_STATE_RUN);
 178
 179         /*
 180          * Since UNPACK enable is set in io mode register, populate 2 tags
 181          * for each fifo register.
 182          *
 183          * Create the first tag as follows, with the start tag and first byte
 184          * of the data to be written
 185          *      +--------+--------+--------+--------+
 186          *      | STOP / |  data  | START  | ADDR   |
 187          *      |DATA tag|  byte  |  tag   | << 1   |
 188          *      +--------+--------+--------+--------+
 189          * rest will be created in the following while loop.
 190          */
 191         tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq,
 192                                         data_ptr[idx]);
 193         tag = ((tag << 16) & 0xffff0000) |
 194                         (QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr));
 195         data_len--;
 196         idx++;
 197
 198         qup_write32(fifo, tag);
 199
 200         stopwatch_init_usecs_expire(&timeout, CONFIG_I2C_TRANSFER_TIMEOUT_US);
 201         while (data_len) {
 202                 tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq,
 203                                                 data_ptr[idx]);
 204                 data_len--;
 205                 idx++;
 206
 207                 if (data_len) {
 208                         tag |= qup_i2c_create_output_tag(
 209                                                 data_len == 1 && stop_seq,
 210                                                 data_ptr[idx]) << 16;
 211                         data_len--;
 212                         idx++;
 213                 }
 214
 215                 qup_write32(fifo, tag);
 216
 217                 ret = qup_i2c_write_fifo_flush(id, &timeout);
 218
 219                 if (ret) {
 220                         printk(QUPDBG "%s: error\n", __func__);
 221                         return ret;
 222                 }
 223         }
 224
 225         ret = qup_i2c_write_fifo_flush(id, &timeout);
 226
 227         qup_set_state(id, QUP_STATE_RESET);
 228
 229         return ret;
 230 }
 231
 232 static qup_return_t qup_i2c_write(blsp_qup_id_t id, uint8_t mode,
 233                                   qup_data_t *p_tx_obj, uint8_t stop_seq)
 234 {
 235         qup_return_t ret = QUP_ERR_UNDEFINED;
 236
 237         switch (mode) {
 238         case QUP_MODE_FIFO:
 239         case QUP_MODE_BLOCK:
 240                 ret = qup_i2c_write_fifo(id, p_tx_obj, stop_seq);
 241                 break;
 242         default:
 243                 ret = QUP_ERR_UNSUPPORTED;
 244         }
 245
 246         if (ret) {
 247                 qup_set_state(id, QUP_STATE_RESET);
 248                 printk(QUPDBG "%s() failed (%d)\n", __func__, ret);
 249         }
 250
 251         return ret;
 252 }
 253
 254 static int qup_i2c_parse_tag(uint32_t data, uint8_t *data_ptr, uint32_t len)
 255 {
 256         int i, idx = 0;
 257         int max = (len > 2) ? 2 : len;
 258
 259         for (i = 0; i < max; i++) {
 260                 switch (QUP_I2C_MI_TAG(data)) {
 261                 case QUP_I2C_MIDATA_SEQ:
 262                         data_ptr[idx] = QUP_I2C_DATA(data);
 263                         idx++;
 264                         break;
 265                 case QUP_I2C_MISTOP_SEQ:
 266                         data_ptr[idx] = QUP_I2C_DATA(data);
 267                         idx++;
 268                         return idx;
 269                 default:
 270                         printk(QUPDBG "%s: Unexpected tag (0x%x)\n", __func__,
 271                                 QUP_I2C_MI_TAG(data));
 272                         return -1;
 273                 }
 274
 275                 data = (data >> 16);
 276         }
 277
 278         return idx;
 279 }
 280
 281 static qup_return_t qup_i2c_read_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj)
 282 {
 283         qup_return_t ret = QUP_ERR_UNDEFINED;
 284         uint8_t addr = p_tx_obj->p.iic.addr;
 285         uint8_t *data_ptr = p_tx_obj->p.iic.data;
 286         unsigned int data_len = p_tx_obj->p.iic.data_len;
 287         unsigned int idx = 0;
 288         uint32_t *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO);
 289         struct stopwatch timeout;
 290
 291         qup_reset_master_status(id);
 292
 293         qup_write32(QUP_ADDR(id, QUP_IO_MODES),
 294                 QUP_UNPACK_EN | QUP_PACK_EN |
 295                           ((QUP_MODE_BLOCK & QUP_MODE_MASK) <<
 296                                         QUP_OUTPUT_MODE_SHFT) |
 297                           ((QUP_MODE_BLOCK & QUP_MODE_MASK) <<
 298                                         QUP_INPUT_MODE_SHFT));
 299
 300         qup_write32(QUP_ADDR(id, QUP_MX_INPUT_COUNT), data_len);
 301
 302         qup_set_state(id, QUP_STATE_RUN);
 303
 304         qup_write32(fifo, (QUP_I2C_START_SEQ |
 305                                   (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ)) |
 306                                 ((QUP_I2C_RECV_SEQ | data_len) << 16));
 307
 308         stopwatch_init_usecs_expire(&timeout, CONFIG_I2C_TRANSFER_TIMEOUT_US);
 309         ret = qup_i2c_write_fifo_flush(id, &timeout);
 310         if (ret) {
 311                 printk(QUPDBG "%s: OUTPUT_FIFO_NOT_EMPTY\n", __func__);
 312                 return ret;
 313         }
 314
 315         ret = qup_fifo_wait_for(id, INPUT_SERVICE_FLAG, &timeout);
 316         if (ret) {
 317                 printk(QUPDBG "%s: INPUT_SERVICE_FLAG\n", __func__);
 318                 return ret;
 319         }
 320
 321         fifo = QUP_ADDR(id, QUP_INPUT_FIFO);
 322
 323         while (data_len) {
 324                 uint32_t data;
 325                 int count;
 326
 327                 data = read32(fifo);
 328                 mdelay(1);
 329
 330                 count = qup_i2c_parse_tag(data, data_ptr + idx, data_len);
 331
 332                 if (count < 0) {
 333                         printk(QUPDBG "%s: Cannot parse tag 0x%x\n",
 334                                                 __func__, data);
 335                         qup_set_state(id, QUP_STATE_PAUSE);
 336
 337                         return QUP_ERR_I2C_INVALID_TAG;
 338                 }
 339
 340                 idx += count;
 341                 data_len -= count;
 342
 343                 qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), INPUT_SERVICE_FLAG);
 344         }
 345
 346         p_tx_obj->p.iic.data_len = idx;
 347
 348         qup_write32(QUP_ADDR(id, QUP_MX_READ_COUNT), 0);
 349
 350         qup_set_state(id, QUP_STATE_RESET);
 351
 352         return QUP_SUCCESS;
 353 }
 354
 355 static qup_return_t qup_i2c_read(blsp_qup_id_t id, uint8_t mode,
 356                                  qup_data_t *p_tx_obj)
 357 {
 358         qup_return_t ret = QUP_ERR_UNDEFINED;
 359
 360         qup_set_state(id, QUP_STATE_RESET);
 361
 362         switch (mode) {
 363         case QUP_MODE_FIFO:
 364         case QUP_MODE_BLOCK:
 365                 ret = qup_i2c_read_fifo(id, p_tx_obj);
 366                 break;
 367         default:
 368                 ret = QUP_ERR_UNSUPPORTED;
 369         }
 370
 371         if (ret) {
 372                 qup_set_state(id, QUP_STATE_RESET);
 373                 printk(QUPDBG "%s() failed (%d)\n", __func__, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 qup_return_t qup_init(blsp_qup_id_t id, const qup_config_t *config_ptr)
 380 {
 381         qup_return_t ret = QUP_ERR_UNDEFINED;
 382         uint32_t reg_val;
 383
 384         /* Reset the QUP core.*/
 385         qup_write32(QUP_ADDR(id, QUP_SW_RESET), 0x1);
 386
 387         /* Wait till the reset takes effect */
 388         ret = qup_wait_for_state(id, QUP_STATE_RESET);
 389         if (ret)
 390                 goto bailout;
 391
 392         /* Reset the config */
 393         qup_write32(QUP_ADDR(id, QUP_CONFIG), 0);
 394
 395         /* Program the config register */
 396         /* Set N value */
 397         reg_val = 0x0F;
 398         /* Set protocol */
 399         switch (config_ptr->protocol) {
 400         case QUP_MINICORE_I2C_MASTER:
 401                 reg_val |= ((config_ptr->protocol &
 402                                 QUP_MINI_CORE_PROTO_MASK) <<
 403                                 QUP_MINI_CORE_PROTO_SHFT);
 404                 break;
 405         default:
 406                 ret = QUP_ERR_UNSUPPORTED;
 407                 goto bailout;
 408         }
 409         reg_val |= QUP_APP_CLK_ON_EN | QUP_CORE_CLK_ON_EN;
 410         qup_write32(QUP_ADDR(id, QUP_CONFIG), reg_val);
 411
 412         /* Choose version 1 tag */
 413         qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CONFIG), 0);
 414
 415         /* Reset i2c clk cntl register */
 416         qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), 0);
 417
 418         /* Set QUP IO Mode */
 419         switch (config_ptr->mode) {
 420         case QUP_MODE_FIFO:
 421         case QUP_MODE_BLOCK:
 422                 reg_val = QUP_UNPACK_EN | QUP_PACK_EN |
 423                           ((config_ptr->mode & QUP_MODE_MASK) <<
 424                                         QUP_OUTPUT_MODE_SHFT) |
 425                           ((config_ptr->mode & QUP_MODE_MASK) <<
 426                                         QUP_INPUT_MODE_SHFT);
 427                 break;
 428         default:
 429                 ret = QUP_ERR_UNSUPPORTED;
 430                 goto bailout;
 431         }
 432         qup_write32(QUP_ADDR(id, QUP_IO_MODES), reg_val);
 433
 434         /*Set i2c clk cntl*/
 435         reg_val = (QUP_DIVIDER_MIN_VAL << QUP_HS_DIVIDER_SHFT);
 436         reg_val |= ((((config_ptr->src_frequency / config_ptr->clk_frequency)
 437                         / 2) - QUP_DIVIDER_MIN_VAL) &
 438                                 QUP_FS_DIVIDER_MASK);
 439         qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), reg_val);
 440
 441         qup_set_state(id, QUP_STATE_RESET);
 442 bailout:
 443         if (ret)
 444                 printk(QUPDBG "failed to init qup (%d)\n", ret);
 445
 446         return ret;
 447 }
 448
 449 qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state)
 450 {
 451         qup_return_t ret = QUP_ERR_UNDEFINED;
 452         unsigned int curr_state = read32(QUP_ADDR(id, QUP_STATE));
 453
 454         if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) {
 455                 /*
 456                 * For PAUSE_STATE to RESET_STATE transition,
 457                 * two writes of  10[binary]) are required for the
 458                 * transition to complete.
 459                 */
 460                 if (QUP_STATE_PAUSE == curr_state && QUP_STATE_RESET == state) {
 461                         qup_write32(QUP_ADDR(id, QUP_STATE), 0x2);
 462                         qup_write32(QUP_ADDR(id, QUP_STATE), 0x2);
 463                 } else {
 464                         qup_write32(QUP_ADDR(id, QUP_STATE), state);
 465                 }
 466                 ret = qup_wait_for_state(id, state);
 467         }
 468
 469         return ret;
 470 }
 471
 472 static qup_return_t qup_i2c_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj,
 473                                       uint8_t stop_seq)
 474 {
 475         qup_return_t ret = QUP_ERR_UNDEFINED;
 476         uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >>
 477                         QUP_OUTPUT_MODE_SHFT) & QUP_MODE_MASK;
 478
 479         ret = qup_i2c_write(id, mode, p_tx_obj, stop_seq);
 480         if (QUP_DEBUG) {
 481                 int i;
 482
 483                 printk(BIOS_DEBUG, "i2c tx bus %d device %2.2x:",
 484                        id, p_tx_obj->p.iic.addr);
 485                 for (i = 0; i < p_tx_obj->p.iic.data_len; i++)
 486                         printk(BIOS_DEBUG, " %2.2x", p_tx_obj->p.iic.data[i]);
 487                 printk(BIOS_DEBUG, "\n");
 488         }
 489
 490         return ret;
 491 }
 492
 493 qup_return_t qup_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj,
 494                            uint8_t stop_seq)
 495 {
 496         qup_return_t ret = QUP_ERR_UNDEFINED;
 497
 498         if (p_tx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >>
 499                         QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) {
 500                 switch (p_tx_obj->protocol) {
 501                 case QUP_MINICORE_I2C_MASTER:
 502                         ret = qup_i2c_send_data(id, p_tx_obj, stop_seq);
 503                         break;
 504                 default:
 505                         ret = QUP_ERR_UNSUPPORTED;
 506                 }
 507         }
 508
 509         return ret;
 510 }
 511
 512 static qup_return_t qup_i2c_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj)
 513 {
 514         qup_return_t ret = QUP_ERR_UNDEFINED;
 515         uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >>
 516                         QUP_INPUT_MODE_SHFT) & QUP_MODE_MASK;
 517
 518         ret = qup_i2c_read(id, mode, p_rx_obj);
 519         if (QUP_DEBUG) {
 520                 int i;
 521
 522                 printk(BIOS_DEBUG, "i2c rxed on bus %d device %2.2x:",
 523                        id, p_rx_obj->p.iic.addr);
 524                 for (i = 0; i < p_rx_obj->p.iic.data_len; i++)
 525                         printk(BIOS_DEBUG, " %2.2x", p_rx_obj->p.iic.data[i]);
 526                 printk(BIOS_DEBUG, "\n");
 527         }
 528
 529         return ret;
 530 }
 531
 532 qup_return_t qup_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj)
 533 {
 534         qup_return_t ret = QUP_ERR_UNDEFINED;
 535
 536         if (p_rx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >>
 537                         QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) {
 538                 switch (p_rx_obj->protocol) {
 539                 case QUP_MINICORE_I2C_MASTER:
 540                         ret = qup_i2c_recv_data(id, p_rx_obj);
 541                         break;
 542                 default:
 543                         ret = QUP_ERR_UNSUPPORTED;
 544                 }
 545         }
 546
 547         return ret;
 548 }