src/soc/samsung/exynos5420/alternate_cbfs.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/cache.h>
   4 #include <boot_device.h>
   5 #include <console/console.h>
   6 #include <soc/alternate_cbfs.h>
   7 #include <soc/power.h>
   8 #include <soc/spi.h>
   9 #include <symbols.h>
  10
  11 /* This allows USB A-A firmware upload from a compatible host in four parts:
  12  * The first two are the bare BL1 and the coreboot boot block, which are just
  13  * written to their respective loading addresses. These transfers are initiated
  14  * by the IROM / BL1, so this code has nothing to do with them.
  15  *
  16  * The third transfer is a valid CBFS image that contains only the romstage,
  17  * and must be small enough to fit into the PRE_RAM CBFS cache in
  18  * IRAM. It is loaded when this function gets called in the boot block, and
  19  * the normal CBFS code extracts the romstage from it.
  20  *
  21  * The fourth transfer is also a CBFS image, but can be of arbitrary size and
  22  * should contain all available stages/payloads/etc. It is loaded when this
  23  * function is called a second time at the end of the romstage, and copied to
  24  * the romstage/ramstage CBFS cache in DRAM. It will reside there for the
  25  * rest of the firmware's lifetime and all subsequent stages can just directly
  26  * reference it there.
  27  */
  28 static int usb_cbfs_open(void)
  29 {
  30         if (!ENV_ROMSTAGE_OR_BEFORE)
  31                 return 0;
  32
  33         static int first_run = 1;
  34         int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr;
  35
  36         if (!first_run)
  37                 return 0;
  38
  39         dcache_mmu_disable();
  40         if (!irom_load_usb()) {
  41                 dcache_mmu_enable();
  42                 printk(BIOS_EMERG, "Unable to load CBFS image via USB!\n");
  43                 return -1;
  44         }
  45         dcache_mmu_enable();
  46
  47         /*
  48          * We need to trust the host/irom to copy the image to our
  49          * _cbfs_cache address... there is no way to control or even
  50          * check the transfer size or target address from our side.
  51          */
  52
  53         printk(BIOS_DEBUG, "USB A-A transfer successful, CBFS image should now"
  54                 " be at %p\n", _cbfs_cache);
  55         first_run = 0;
  56         return 0;
  57 }
  58
  59 /*
  60  * SDMMC works very similar to USB A-A: we copy the CBFS image into memory
  61  * and read it from there. While SDMMC would also allow direct block by block
  62  * on-demand reading, we might run into problems if we call back into the IROM
  63  * in very late boot stages (e.g. after initializing/changing MMC clocks)... so
  64  * this seems like a safer approach. It also makes it easy to pass our image
  65  * down to payloads.
  66  */
  67 static int sdmmc_cbfs_open(void)
  68 {
  69         if (!ENV_ROMSTAGE_OR_BEFORE)
  70                 return 0;
  71
  72         /*
  73          * In the bootblock, we just copy the small part that fits in the buffer
  74          * and hope that it's enough (since the romstage is currently always the
  75          * first component in the image, this should work out). In the romstage,
  76          * we copy until our cache is full (currently 12M) to avoid the pain of
  77          * figuring out the true image size from in here. Since this is mainly a
  78          * developer/debug boot mode, those shortcomings should be bearable.
  79          */
  80         const u32 count = REGION_SIZE(cbfs_cache) / 512;
  81         static int first_run = 1;
  82         int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) =
  83                 *irom_sdmmc_read_blocks_ptr;
  84
  85         if (!first_run)
  86                 return 0;
  87
  88         dcache_mmu_disable();
  89         if (!irom_load_sdmmc(1, count, _cbfs_cache)) {
  90                 dcache_mmu_enable();
  91                 printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n");
  92                 return -1;
  93         }
  94         dcache_mmu_enable();
  95
  96         printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be"
  97                 " at %p\n", _cbfs_cache);
  98         first_run = 0;
  99         return 0;
 100 }
 101
 102 static struct mem_region_device alternate_rdev =
 103         MEM_REGION_DEV_RO_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache));
 104
 105 const struct region_device *boot_device_ro(void)
 106 {
 107         if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
 108                 return &alternate_rdev.rdev;
 109
 110         switch (exynos_power->om_stat & OM_STAT_MASK) {
 111         case OM_STAT_SDMMC:
 112                 return &alternate_rdev.rdev;
 113         case OM_STAT_SPI:
 114                 return exynos_spi_boot_device();
 115         default:
 116                 printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
 117                         exynos_power->om_stat);
 118                 return NULL;
 119         }
 120 }
 121
 122 void boot_device_init(void)
 123 {
 124         if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) {
 125                 printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
 126                 usb_cbfs_open();
 127                 return;
 128         }
 129
 130         switch (exynos_power->om_stat & OM_STAT_MASK) {
 131         case OM_STAT_SDMMC:
 132                 printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
 133                 sdmmc_cbfs_open();
 134                 break;
 135         case OM_STAT_SPI:
 136                 exynos_init_spi_boot_device();
 137                 break;
 138         default:
 139                 printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
 140                         exynos_power->om_stat);
 141         }
 142 }