src/soc/samsung/exynos5420/spi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <assert.h>
   5 #include <cbfs.h>
   6 #include <console/console.h>
   7 #include <soc/cpu.h>
   8 #include <soc/spi.h>
   9 #include <spi-generic.h>
  10 #include <stddef.h>
  11 #include <stdint.h>
  12 #include <string.h>
  13 #include <symbols.h>
  14
  15 #define EXYNOS_SPI_MAX_TRANSFER_BYTES (65535)
  16
  17 #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI
  18 # define DEBUG_SPI(x,...)       printk(BIOS_DEBUG, "EXYNOS_SPI: " x)
  19 #else
  20 # define DEBUG_SPI(x,...)
  21 #endif
  22
  23 struct exynos_spi_slave {
  24         struct spi_slave slave;
  25         struct exynos_spi *regs;
  26         int initialized;
  27 };
  28
  29 /* TODO(hungte) Move the SPI param list to per-board configuration, probably
  30  * Kconfig or mainboard.c */
  31 static struct exynos_spi_slave exynos_spi_slaves[3] = {
  32         // SPI 0
  33         {
  34                 .slave = { .bus = 0, },
  35                 .regs = (void *)EXYNOS5_SPI0_BASE,
  36         },
  37         // SPI 1
  38         {
  39                 .slave = { .bus = 1, },
  40                 .regs = (void *)EXYNOS5_SPI1_BASE,
  41         },
  42         // SPI 2
  43         {
  44                 .slave = { .bus = 2, },
  45                 .regs = (void *)EXYNOS5_SPI2_BASE,
  46         },
  47 };
  48
  49 static inline struct exynos_spi_slave *to_exynos_spi(const struct spi_slave *slave)
  50 {
  51         return &exynos_spi_slaves[slave->bus];
  52 }
  53
  54 static void spi_sw_reset(struct exynos_spi *regs, int word)
  55 {
  56         const uint32_t orig_mode_cfg = read32(&regs->mode_cfg);
  57         uint32_t mode_cfg = orig_mode_cfg;
  58         const uint32_t orig_swap_cfg = read32(&regs->swap_cfg);
  59         uint32_t swap_cfg = orig_swap_cfg;
  60
  61         mode_cfg &= ~(SPI_MODE_CH_WIDTH_MASK | SPI_MODE_BUS_WIDTH_MASK);
  62         if (word) {
  63                 mode_cfg |= SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD;
  64                 swap_cfg |= SPI_RX_SWAP_EN |
  65                             SPI_RX_BYTE_SWAP |
  66                             SPI_RX_HWORD_SWAP |
  67                             SPI_TX_SWAP_EN |
  68                             SPI_TX_BYTE_SWAP |
  69                             SPI_TX_HWORD_SWAP;
  70         } else {
  71                 mode_cfg |= SPI_MODE_CH_WIDTH_BYTE | SPI_MODE_BUS_WIDTH_BYTE;
  72                 swap_cfg = 0;
  73         }
  74
  75         if (mode_cfg != orig_mode_cfg)
  76                 write32(&regs->mode_cfg, mode_cfg);
  77         if (swap_cfg != orig_swap_cfg)
  78                 write32(&regs->swap_cfg, swap_cfg);
  79
  80         clrbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
  81         setbits32(&regs->ch_cfg, SPI_CH_RST);
  82         clrbits32(&regs->ch_cfg, SPI_CH_RST);
  83         setbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
  84 }
  85
  86 static void exynos_spi_init(struct exynos_spi *regs)
  87 {
  88         // Set FB_CLK_SEL.
  89         write32(&regs->fb_clk, SPI_FB_DELAY_180);
  90         // CPOL: Active high.
  91         clrbits32(&regs->ch_cfg, SPI_CH_CPOL_L);
  92
  93         // Clear rx and tx channel if set previously.
  94         clrbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
  95
  96         setbits32(&regs->swap_cfg,
  97                      SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP);
  98         clrbits32(&regs->ch_cfg, SPI_CH_HS_EN);
  99
 100         // Do a soft reset, which will also enable both channels.
 101         spi_sw_reset(regs, 1);
 102 }
 103
 104 static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
 105 {
 106         struct exynos_spi *regs = to_exynos_spi(slave)->regs;
 107         // TODO(hungte) Add some delay if too many transactions happen at once.
 108         clrbits32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);
 109         return 0;
 110 }
 111
 112 static void spi_transfer(struct exynos_spi *regs, void *in, const void *out,
 113                          size_t size)
 114 {
 115         u8 *inb = in;
 116         const u8 *outb = out;
 117
 118         size_t width = (size % 4) ? 1 : 4;
 119
 120         while (size) {
 121                 size_t packets = size / width;
 122                 // The packet count field is 16 bits wide.
 123                 packets = MIN(packets, (1 << 16) - 1);
 124
 125                 size_t out_bytes, in_bytes;
 126                 out_bytes = in_bytes = packets * width;
 127
 128                 spi_sw_reset(regs, width == 4);
 129                 write32(&regs->pkt_cnt, packets | SPI_PACKET_CNT_EN);
 130
 131                 while (out_bytes || in_bytes) {
 132                         uint32_t spi_sts = read32(&regs->spi_sts);
 133                         int rx_lvl = ((spi_sts >> 15) & 0x1ff);
 134                         int tx_lvl = ((spi_sts >> 6) & 0x1ff);
 135
 136                         if (tx_lvl < 32 && tx_lvl < out_bytes) {
 137                                 uint32_t data = 0xffffffff;
 138
 139                                 if (outb) {
 140                                         memcpy(&data, outb, width);
 141                                         outb += width;
 142                                 }
 143                                 write32(&regs->tx_data, data);
 144
 145                                 out_bytes -= width;
 146                         }
 147
 148                         if (rx_lvl >= width) {
 149                                 uint32_t data = read32(&regs->rx_data);
 150
 151                                 if (inb) {
 152                                         memcpy(inb, &data, width);
 153                                         inb += width;
 154                                 }
 155
 156                                 in_bytes -= width;
 157                         }
 158                 }
 159
 160                 size -= packets * width;
 161         }
 162 }
 163
 164 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytes_out,
 165              void *din, size_t bytes_in)
 166 {
 167         struct exynos_spi *regs = to_exynos_spi(slave)->regs;
 168
 169         if (bytes_out && bytes_in) {
 170                 size_t min_size = MIN(bytes_out, bytes_in);
 171
 172                 spi_transfer(regs, din, dout, min_size);
 173
 174                 bytes_out -= min_size;
 175                 bytes_in -= min_size;
 176
 177                 din = (uint8_t *)din + min_size;
 178                 dout = (const uint8_t *)dout + min_size;
 179         }
 180
 181         if (bytes_in)
 182                 spi_transfer(regs, din, NULL, bytes_in);
 183         else if (bytes_out)
 184                 spi_transfer(regs, NULL, dout, bytes_out);
 185
 186         return 0;
 187 }
 188
 189 static void spi_ctrlr_release_bus(const struct spi_slave *slave)
 190 {
 191         struct exynos_spi *regs = to_exynos_spi(slave)->regs;
 192         setbits32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);
 193 }
 194
 195 static int spi_ctrlr_setup(const struct spi_slave *slave)
 196 {
 197         ASSERT(slave->bus < 3);
 198         struct exynos_spi_slave *eslave;
 199
 200         eslave = to_exynos_spi(slave);
 201         if (!eslave->initialized) {
 202                 exynos_spi_init(eslave->regs);
 203                 eslave->initialized = 1;
 204         }
 205         return 0;
 206 }
 207
 208 static const struct spi_ctrlr spi_ctrlr = {
 209         .setup = spi_ctrlr_setup,
 210         .claim_bus = spi_ctrlr_claim_bus,
 211         .release_bus = spi_ctrlr_release_bus,
 212         .xfer = spi_ctrlr_xfer,
 213         .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE,
 214 };
 215
 216 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 217         {
 218                 .ctrlr = &spi_ctrlr,
 219                 .bus_start = 0,
 220                 .bus_end = 2,
 221         },
 222 };
 223
 224 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
 225
 226 static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len,
 227                            uint32_t off)
 228 {
 229         struct exynos_spi *regs = to_exynos_spi(slave)->regs;
 230         u32 command;
 231         spi_claim_bus(slave);
 232
 233         // Send address.
 234         ASSERT(off < (1 << 24));
 235         command = htonl(SF_READ_DATA_CMD << 24 | off);
 236         spi_transfer(regs, NULL, &command, sizeof(command));
 237
 238         // Read the data.
 239         spi_transfer(regs, dest, NULL, len);
 240         spi_release_bus(slave);
 241
 242         return len;
 243 }
 244
 245 static struct exynos_spi_slave *boot_slave;
 246
 247 static ssize_t exynos_spi_readat(const struct region_device *rdev, void *dest,
 248                                         size_t offset, size_t count)
 249 {
 250         DEBUG_SPI("exynos_spi_cbfs_read(%u)\n", count);
 251         return exynos_spi_read(&boot_slave->slave, dest, count, offset);
 252 }
 253
 254 static void *exynos_spi_map(const struct region_device *rdev,
 255                                         size_t offset, size_t count)
 256 {
 257         DEBUG_SPI("exynos_spi_cbfs_map\n");
 258         // exynos: spi_rx_tx may work in 4 byte-width-transmission mode and
 259         // requires buffer memory address to be aligned.
 260         if (count % 4)
 261                 count += 4 - (count % 4);
 262         return mmap_helper_rdev_mmap(rdev, offset, count);
 263 }
 264
 265 static const struct region_device_ops exynos_spi_ops = {
 266         .mmap = exynos_spi_map,
 267         .munmap = mmap_helper_rdev_munmap,
 268         .readat = exynos_spi_readat,
 269 };
 270
 271 static struct mmap_helper_region_device mdev =
 272         MMAP_HELPER_DEV_INIT(&exynos_spi_ops, 0, CONFIG_ROM_SIZE, &cbfs_cache);
 273
 274 void exynos_init_spi_boot_device(void)
 275 {
 276         boot_slave = &exynos_spi_slaves[1];
 277 }
 278
 279 const struct region_device *exynos_spi_boot_device(void)
 280 {
 281         return &mdev.rdev;
 282 }