src/southbridge/intel/i82870/ioapic.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/ioapic.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/pci_ops.h>
   8 #include <types.h>
   9 #include "82870.h"
  10
  11 static void p64h2_ioapic_enable(struct device *dev)
  12 {
  13         /* We have to enable MEM and Bus Master for IOAPIC */
  14         uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  15
  16         pci_write_config16(dev, PCI_COMMAND, command);
  17 }
  18
  19 /**
  20  * Configure one of the IOAPICs in a P64H2.
  21  *
  22  * Note that a PCI bus scan will detect both IOAPICs, so this function
  23  * will be called twice for each P64H2 in the system.
  24  *
  25  * @param dev PCI bus/device/function of P64H2 IOAPIC.
  26  *            NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.
  27  */
  28 static void p64h2_ioapic_init(struct device *dev)
  29 {
  30         uintptr_t memoryBase;
  31
  32         // Read the MBAR address for setting up the IOAPIC in memory space
  33         // NOTE: this address was assigned during enumeration of the bus
  34
  35         memoryBase = (uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
  36
  37         register_new_ioapic(memoryBase);
  38
  39         // Use Processor System Bus to deliver interrupts
  40         ioapic_set_boot_config(memoryBase, true);
  41 }
  42
  43 static struct device_operations ioapic_ops = {
  44         .read_resources   = pci_dev_read_resources,
  45         .set_resources    = pci_dev_set_resources,
  46         .enable_resources = pci_dev_enable_resources,
  47         .init     = p64h2_ioapic_init,
  48         .enable   = p64h2_ioapic_enable,
  49 };
  50
  51 static const struct pci_driver ioapic_driver __pci_driver = {
  52         .ops    = &ioapic_ops,
  53         .vendor = PCI_VID_INTEL,
  54         .device = PCI_DID_INTEL_82870_1E0,
  55
  56 };