soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / superio / fintek / f71863fg / superio.c
blob6f1735d7a25988a83859a16df13bb7225cac6ccf
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <device/device.h>
4 #include <device/pnp.h>
5 #include <superio/conf_mode.h>
6 #include <pc80/keyboard.h>
8 #include "f71863fg.h"
10 static void f71863fg_init(struct device *dev)
12 if (!dev->enabled)
13 return;
15 switch (dev->path.pnp.device) {
16 /* TODO: Might potentially need code for HWM or FDC etc. */
17 case F71863FG_KBC:
18 find_resource(dev, PNP_IDX_IO0);
19 pc_keyboard_init(NO_AUX_DEVICE);
20 break;
24 static struct device_operations ops = {
25 .read_resources = pnp_read_resources,
26 .set_resources = pnp_set_resources,
27 .enable_resources = pnp_enable_resources,
28 .enable = pnp_alt_enable,
29 .init = f71863fg_init,
30 .ops_pnp_mode = &pnp_conf_mode_8787_aa,
33 static struct pnp_info pnp_dev_info[] = {
34 /* TODO: Some of the 0x07f8 etc. values may not be correct. */
35 { NULL, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
36 { NULL, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
37 { NULL, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
38 { NULL, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
39 { NULL, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
40 { NULL, F71863FG_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
41 { NULL, F71863FG_GPIO, },
42 { NULL, F71863FG_VID, PNP_IO0, 0x07f8, },
43 { NULL, F71863FG_SPI, },
44 { NULL, F71863FG_PME, },
47 static void enable_dev(struct device *dev)
49 pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
52 struct chip_operations superio_fintek_f71863fg_ops = {
53 .name = "Fintek F71863FG Super I/O",
54 .enable_dev = enable_dev