1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <cpu/x86/mtrr.h>
4 #include <cpu/x86/cr.h>
5 #include <cpu/x86/cache.h>
7 /* Place the stack in the bss section. It's not necessary to define it in
8 * the linker script. */
9 .section .bss, "aw", @nobits
15 .space CONFIG_STACK_SIZE
17 .set _stack_size, _estack - _stack
22 /* Assume stack alignment doesn't matter here as chipset_teardown_car
23 is expected to be implemented in assembly. */
25 /* Migrate GDT to this text segment */
34 movabs %rax, _cbmem_top_ptr
36 /* The return argument is at 0(%esp), the calling argument at 4(%esp) */
38 movl %eax, _cbmem_top_ptr
40 /* Make sure _cbmem_top_ptr hits dram before invd */
43 btl $CPUID_FEATURE_CLFLUSH_BIT, %edx
46 movabs $_cbmem_top_ptr, %rax
49 clflush _cbmem_top_ptr
53 /* chipset_teardown_car() is expected to disable cache-as-ram. */
54 call chipset_teardown_car
56 /* Enable caching if not already enabled. */
59 and $(~(CR0_CD | CR0_NW)), %eax
63 and $(~(CR0_CD | CR0_NW)), %eax
66 /* Ensure cache is clean. */
71 /* Align stack to 16 bytes at call instruction. */
72 movq $0xfffffffffffffff0, %rax
75 /* Align stack to 16 bytes at call instruction. */
76 andl $0xfffffff0, %esp
79 /* Call this in assembly as some platforms like to mess with the bootflow and
80 call into main directly from chipset_teardown_car. */
81 call postcar_mtrr_setup
83 /* Call into main for postcar. */
85 /* Should never return. */