src/include/cpu/intel/post_codes.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef CPU_INTEL_CAR_POST_CODES_H
   4 #define CPU_INTEL_CAR_POST_CODES_H
   5
   6 #define POSTCODE_SOC_SET_DEF_MTRR_TYPE                  0x21
   7 #define POSTCODE_SOC_CLEAR_FIXED_MTRRS                  0x22    // Intentional Duplicate
   8 #define POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS            0x22
   9 #define POSTCODE_SOC_BSP_INIT                           0x23
  10 #define POSTCODE_SOC_COUNT_CORES                        0x24
  11 #define POSTCODE_SOC_CPU_HYPER_THREADING                0x25
  12 #define POSTCODE_SOC_CPU_SIBLING_DELAY                  0x26
  13 #define POSTCODE_SOC_CPU_AP_INIT                        0x27
  14 #define POSTCODE_SOC_SET_MTRR_BASE                      0x28
  15 #define POSTCODE_SOC_SET_MTRR_MASK                      0x29    // Intentional Duplicate
  16 #define POSTCODE_SOC_AP_HALT                            0x29
  17 #define POSTCODE_SOC_SET_CAR_BASE                       0x2a
  18 #define POSTCODE_SOC_ENABLE_MTRRS                       0x2b
  19 #define POSTCODE_SOC_ENABLE_CACHE                       0x2c
  20 #define POSTCODE_SOC_DISABLE_CACHE                      0x2d
  21 #define POSTCODE_SOC_FILL_CACHE                         0x2e
  22 #define POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY               0x2f
  23
  24 #define POSTCODE_POSTCAR_DISABLE_CACHE                  0x30
  25 #define POSTCODE_POSTCAR_DISABLE_DEF_MTRR               0x31
  26 #define POSTCODE_POSTCAR_TEARDOWN_DONE                  0x32
  27
  28 #endif