util/intelmetool/me.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef ME_H
   4 #define ME_H
   5
   6 #include <inttypes.h>
   7 #include <pci/pci.h>
   8
   9 #define ME_RETRY                100000  /* 1 second */
  10 #define ME_DELAY                10      /* 10 us */
  11
  12 #pragma pack(1)
  13
  14 /*
  15  * Management Engine PCI registers
  16  */
  17
  18 #define PCI_ME_HFS              0x40
  19 #define  ME_HFS_CWS_RESET       0
  20 #define  ME_HFS_CWS_INIT        1
  21 #define  ME_HFS_CWS_REC         2
  22 #define  ME_HFS_CWS_TEST        3
  23 #define  ME_HFS_CWS_DISABLED    4
  24 #define  ME_HFS_CWS_NORMAL      5
  25 #define  ME_HFS_CWS_WAIT        6
  26 #define  ME_HFS_CWS_TRANS       7
  27 #define  ME_HFS_CWS_INVALID     8
  28 #define  ME_HFS_STATE_PREBOOT   0
  29 #define  ME_HFS_STATE_M0_UMA    1
  30 #define  ME_HFS_STATE_M3        4
  31 #define  ME_HFS_STATE_M0        5
  32 #define  ME_HFS_STATE_BRINGUP   6
  33 #define  ME_HFS_STATE_ERROR     7
  34 #define  ME_HFS_ERROR_NONE      0
  35 #define  ME_HFS_ERROR_UNCAT     1
  36 #define  ME_HFS_ERROR_DISABLED  2
  37 #define  ME_HFS_ERROR_IMAGE     3
  38 #define  ME_HFS_ERROR_DEBUG     4
  39 #define  ME_HFS_MODE_NORMAL     0
  40 #define  ME_HFS_MODE_DEBUG      2
  41 #define  ME_HFS_MODE_DIS        3
  42 #define  ME_HFS_MODE_OVER_JMPR  4
  43 #define  ME_HFS_MODE_OVER_MEI   5
  44 #define  ME_HFS_BIOS_DRAM_ACK   1
  45 #define  ME_HFS_ACK_NO_DID      0
  46 #define  ME_HFS_ACK_RESET       1
  47 #define  ME_HFS_ACK_PWR_CYCLE   2
  48 #define  ME_HFS_ACK_S3          3
  49 #define  ME_HFS_ACK_S4          4
  50 #define  ME_HFS_ACK_S5          5
  51 #define  ME_HFS_ACK_GBL_RESET   6
  52 #define  ME_HFS_ACK_CONTINUE    7
  53
  54 struct me_hfs {
  55         uint32_t working_state: 4;
  56         uint32_t mfg_mode: 1;
  57         uint32_t fpt_bad: 1;
  58         uint32_t operation_state: 3;
  59         uint32_t fw_init_complete: 1;
  60         uint32_t ft_bup_ld_flr: 1;
  61         uint32_t update_in_progress: 1;
  62         uint32_t error_code: 4;
  63         uint32_t operation_mode: 4;
  64         uint32_t reserved: 4;
  65         uint32_t boot_options_present: 1;
  66         uint32_t ack_data: 3;
  67         uint32_t bios_msg_ack: 4;
  68 } __attribute__((packed));
  69
  70 #define PCI_ME_UMA              0x44
  71
  72 struct me_uma {
  73         uint32_t size: 6;
  74         uint32_t reserved_1: 10;
  75         uint32_t valid: 1;
  76         uint32_t reserved_0: 14;
  77         uint32_t set_to_one: 1;
  78 } __attribute__((packed));
  79
  80 #define PCI_ME_H_GS             0x4c
  81 #define  ME_INIT_DONE           1
  82 #define  ME_INIT_STATUS_SUCCESS 0
  83 #define  ME_INIT_STATUS_NOMEM   1
  84 #define  ME_INIT_STATUS_ERROR   2
  85
  86 struct me_did {
  87         uint32_t uma_base: 16;
  88         uint32_t reserved: 8;
  89         uint32_t status: 4;
  90         uint32_t init_done: 4;
  91 } __attribute__((packed));
  92
  93 #define PCI_ME_GMES             0x48
  94 #define  ME_GMES_PHASE_ROM      0
  95 #define  ME_GMES_PHASE_BUP      1
  96 #define  ME_GMES_PHASE_UKERNEL  2
  97 #define  ME_GMES_PHASE_POLICY   3
  98 #define  ME_GMES_PHASE_MODULE   4
  99 #define  ME_GMES_PHASE_UNKNOWN  5
 100 #define  ME_GMES_PHASE_HOST     6
 101
 102 struct me_gmes {
 103         uint32_t bist_in_prog : 1;
 104         uint32_t icc_prog_sts : 2;
 105         uint32_t invoke_mebx : 1;
 106         uint32_t cpu_replaced_sts : 1;
 107         uint32_t mbp_rdy : 1;
 108         uint32_t mfs_failure : 1;
 109         uint32_t warm_rst_req_for_df : 1;
 110         uint32_t cpu_replaced_valid : 1;
 111         uint32_t reserved_1 : 2;
 112         uint32_t fw_upd_ipu : 1;
 113         uint32_t reserved_2 : 4;
 114         uint32_t current_state: 8;
 115         uint32_t current_pmevent: 4;
 116         uint32_t progress_code: 4;
 117 } __attribute__((packed));
 118
 119 #define PCI_ME_HERES            0xbc
 120 #define  PCI_ME_EXT_SHA1        0x00
 121 #define  PCI_ME_EXT_SHA256      0x02
 122 #define PCI_ME_HER(x)           (0xc0+(4*(x)))
 123
 124 struct me_heres {
 125         uint32_t extend_reg_algorithm: 4;
 126         uint32_t reserved: 26;
 127         uint32_t extend_feature_present: 1;
 128         uint32_t extend_reg_valid: 1;
 129 } __attribute__((packed));
 130
 131 struct me_thermal_reporting {
 132         uint32_t polling_timeout: 8;
 133         uint32_t smbus_ec_msglen: 8;
 134         uint32_t smbus_ec_msgpec: 8;
 135         uint32_t dimmnumber: 8;
 136 } __attribute__((packed));
 137
 138 /*
 139  * Management Engine MEI registers
 140  */
 141
 142 #define MEI_H_CB_WW             0x00
 143 #define MEI_H_CSR               0x04
 144 #define MEI_ME_CB_RW            0x08
 145 #define MEI_ME_CSR_HA           0x0c
 146
 147 struct mei_csr {
 148         uint32_t interrupt_enable: 1;
 149         uint32_t interrupt_status: 1;
 150         uint32_t interrupt_generate: 1;
 151         uint32_t ready: 1;
 152         uint32_t reset: 1;
 153         uint32_t reserved: 3;
 154         uint32_t buffer_read_ptr: 8;
 155         uint32_t buffer_write_ptr: 8;
 156         uint32_t buffer_depth: 8;
 157 } __attribute__((packed));
 158
 159 #define MEI_ADDRESS_HBM         0x00
 160 #define MEI_ADDRESS_CORE_WD     0x01
 161 #define MEI_ADDRESS_AMT         0x02
 162 #define MEI_ADDRESS_RESERVED    0x03
 163 #define MEI_ADDRESS_WDT         0x04
 164 #define MEI_ADDRESS_POLICY      0x05
 165 #define MEI_ADDRESS_PASSWORD    0x06
 166 #define MEI_ADDRESS_MKHI        0x07
 167 #define MEI_ADDRESS_ICC         0x08
 168 #define MEI_ADDRESS_THERMAL     0x09
 169 #define MEI_ADDRESS_SPI         0x0a
 170
 171 #define MEI_HOST_ADDRESS        0
 172
 173 struct mei_header {
 174         uint32_t client_address: 8;
 175         uint32_t host_address: 8;
 176         uint32_t length: 9;
 177         uint32_t reserved: 6;
 178         uint32_t is_complete: 1;
 179 } __attribute__((packed));
 180
 181 #define MKHI_GROUP_ID_CBM       0x00
 182 #define MKHI_GROUP_ID_PM        0x01
 183 #define MKHI_GROUP_ID_PWD       0x02
 184 #define MKHI_GROUP_ID_FWCAPS    0x03
 185 #define MKHI_GROUP_ID_APP       0x04
 186 #define MKHI_GROUP_ID_SPI       0x05
 187 #define MKHI_GROUP_ID_MDES      0x08
 188 #define MKHI_GROUP_ID_MAX       0x09
 189 #define MKHI_GROUP_ID_GEN       0xff
 190
 191 #define MKHI_FWCAPS_GET_RULE    0x02
 192 #define MKHI_FWCAPS_SET_RULE    0x03
 193 #define MKHI_GLOBAL_RESET       0x0b
 194
 195 #define GEN_GET_MKHI_VERSION    0x01
 196 #define GEN_GET_FW_VERSION      0x02
 197 #define GEN_UNCONFIG_NO_PWD     0x0d
 198 #define GEN_SET_DEBUG_MEM       0x11
 199
 200 #define FWCAPS_ME_FWU_RULE      0x2e
 201 #define FWCAPS_OVERRIDE         0x14
 202
 203 #define MKHI_THERMAL_REPORTING  0x00
 204 #define MKHI_GET_FW_VERSION     0x02
 205 #define MKHI_MDES_ENABLE        0x09
 206 #define MKHI_END_OF_POST        0x0c
 207 #define MKHI_FEATURE_OVERRIDE   0x14
 208
 209 #define HBM_HOST_START_REQ_CMD                  0x01
 210 #define HBM_HOST_STOP_REQ_CMD                   0x02
 211 #define HBM_ME_STOP_REQ_CMD                     0x03
 212 #define HBM_HOST_ENUM_REQ_CMD                   0x04
 213 #define HBM_HOST_CLIENT_PROPERTIES_REQ_CMD      0x05
 214 #define HBM_CLIENT_CONNECT_REQ_CMD              0x06
 215 #define HBM_CLIENT_DISCONNECT_REQ_CMD           0x07
 216
 217 struct mkhi_header {
 218         uint32_t group_id: 8;
 219         uint32_t command: 7;
 220         uint32_t is_response: 1;
 221         uint32_t reserved: 8;
 222         uint32_t result: 8;
 223 } __attribute__((packed));
 224
 225 struct me_fw_version {
 226         uint16_t code_minor;
 227         uint16_t code_major;
 228         uint16_t code_build_number;
 229         uint16_t code_hot_fix;
 230         uint16_t recovery_minor;
 231         uint16_t recovery_major;
 232         uint16_t recovery_build_number;
 233         uint16_t recovery_hot_fix;
 234         uint16_t fitcminor;
 235         uint16_t fitcmajor;
 236         uint16_t fitcbuildno;
 237         uint16_t fitchotfix;
 238 } __attribute__((packed));
 239
 240
 241 #define HECI_EOP_STATUS_SUCCESS       0x0
 242 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
 243
 244 #define CBM_RR_GLOBAL_RESET     0x01
 245
 246 #define GLOBAL_RESET_BIOS_MRC   0x01
 247 #define GLOBAL_RESET_BIOS_POST  0x02
 248 #define GLOBAL_RESET_MEBX       0x03
 249
 250 struct me_global_reset {
 251         uint8_t request_origin;
 252         uint8_t reset_type;
 253 } __attribute__((packed));
 254
 255 typedef enum {
 256         ME_NORMAL_BIOS_PATH,
 257         ME_S3WAKE_BIOS_PATH,
 258         ME_ERROR_BIOS_PATH,
 259         ME_RECOVERY_BIOS_PATH,
 260         ME_DISABLE_BIOS_PATH,
 261         ME_FIRMWARE_UPDATE_BIOS_PATH,
 262 } me_bios_path;
 263
 264 typedef struct {
 265         uint32_t       major_version  : 16;
 266         uint32_t       minor_version  : 16;
 267         uint32_t       hotfix_version : 16;
 268         uint32_t       build_version  : 16;
 269 } __attribute__((packed)) mbp_fw_version_name;
 270
 271 typedef struct {
 272         uint8_t        num_icc_profiles;
 273         uint8_t        icc_profile_soft_strap;
 274         uint8_t        icc_profile_index;
 275         uint8_t        reserved;
 276         uint32_t       register_lock_mask[3];
 277 } __attribute__((packed)) mbp_icc_profile;
 278
 279 typedef struct {
 280         uint32_t  full_net              : 1;
 281         uint32_t  std_net               : 1;
 282         uint32_t  manageability : 1;
 283         uint32_t  small_business        : 1;
 284         uint32_t  l3manageability       : 1;
 285         uint32_t  intel_at              : 1;
 286         uint32_t  intel_cls             : 1;
 287         uint32_t  reserved              : 3;
 288         uint32_t  intel_mpc             : 1;
 289         uint32_t  icc_over_clocking     : 1;
 290         uint32_t  pavp          : 1;
 291         uint32_t  reserved_1            : 4;
 292         uint32_t  ipv6          : 1;
 293         uint32_t  kvm           : 1;
 294         uint32_t  och           : 1;
 295         uint32_t  vlan          : 1;
 296         uint32_t  tls           : 1;
 297         uint32_t  reserved_4            : 1;
 298         uint32_t  wlan          : 1;
 299         uint32_t  reserved_5            : 8;
 300 } __attribute__((packed)) mefwcaps_sku;
 301
 302 typedef struct {
 303         uint16_t  lock_state                 : 1;
 304         uint16_t  authenticate_module     : 1;
 305         uint16_t  s3authentication           : 1;
 306         uint16_t  flash_wear_out          : 1;
 307         uint16_t  flash_variable_security : 1;
 308         uint16_t  wwan3gpresent      : 1;
 309         uint16_t  wwan3goob                  : 1;
 310         uint16_t  reserved                   : 9;
 311 } __attribute__((packed)) tdt_state_flag;
 312
 313 typedef struct {
 314         uint8_t           state;
 315         uint8_t           last_theft_trigger;
 316         tdt_state_flag  flags;
 317 }  __attribute__((packed)) tdt_state_info;
 318
 319 typedef struct {
 320         uint32_t  platform_target_usage_type     : 4;
 321         uint32_t  platform_target_market_type : 2;
 322         uint32_t  super_sku                      : 1;
 323         uint32_t  reserved                       : 1;
 324         uint32_t  intel_me_fw_image_type         : 4;
 325         uint32_t  platform_brand                 : 4;
 326         uint32_t  reserved_1                     : 16;
 327 }  __attribute__((packed)) platform_type_rule_data;
 328
 329 typedef struct {
 330         mefwcaps_sku fw_capabilities;
 331         uint8_t      available;
 332 } mbp_fw_caps;
 333
 334 typedef struct {
 335         uint16_t        device_id;
 336         uint16_t        fuse_test_flags;
 337         uint32_t        umchid[4];
 338 }  __attribute__((packed)) mbp_rom_bist_data;
 339
 340 typedef struct {
 341         uint32_t        key[8];
 342 } mbp_platform_key;
 343
 344 typedef struct {
 345         platform_type_rule_data rule_data;
 346         uint8_t           available;
 347 } mbp_plat_type;
 348
 349 typedef struct {
 350         mbp_fw_version_name fw_version_name;
 351         mbp_fw_caps         fw_caps_sku;
 352         mbp_rom_bist_data   rom_bist_data;
 353         mbp_platform_key    platform_key;
 354         mbp_plat_type       fw_plat_type;
 355         mbp_icc_profile     icc_profile;
 356         tdt_state_info      at_state;
 357         uint32_t                    mfsintegrity;
 358 } me_bios_payload;
 359
 360 typedef  struct {
 361         uint32_t  mbp_size       : 8;
 362         uint32_t  num_entries : 8;
 363         uint32_t  rsvd           : 16;
 364 } __attribute__((packed)) mbp_header;
 365
 366 typedef struct {
 367         uint32_t  app_id  : 8;
 368         uint32_t  item_id : 8;
 369         uint32_t  length  : 8;
 370         uint32_t  rsvd    : 8;
 371 }  __attribute__((packed)) mbp_item_header;
 372
 373 struct me_fwcaps {
 374         uint32_t id;
 375         uint8_t length;
 376         mefwcaps_sku caps_sku;
 377         uint8_t reserved[3];
 378 } __attribute__((packed));
 379
 380 struct me_debug_mem {
 381         uint32_t debug_phys;
 382         uint32_t debug_size;
 383         uint32_t me_phys;
 384         uint32_t me_size;
 385 } __attribute__((packed));
 386
 387 void intel_me_status(uint32_t hfs, uint32_t gmes);
 388 void mkhi_thermal(void);
 389 uint32_t intel_mei_setup(struct pci_dev *dev);
 390 void intel_mei_unmap(void);
 391 int mkhi_get_fwcaps(void);
 392 int mkhi_get_fw_version(int *major, int *minor);
 393 int mkhi_debug_me_memory(void *addr);
 394 void mei_reset(void);
 395 int intel_me_extend_valid(struct pci_dev *dev);
 396
 397 #endif