util/msrtool/intel_pentium4_early.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include "msrtool.h"
   4
   5 int intel_pentium4_early_probe(const struct targetdef *target, const struct cpuid_t *id) {
   6         return ((VENDOR_INTEL == id->vendor) &&
   7                 (0xf == id->family) &&
   8                 (0x2 == id->model));
   9 }
  10
  11 const struct msrdef intel_pentium4_early_msrs[] = {
  12         {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", "", {
  13                 { BITS_EOT }
  14         }},
  15         {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", "", {
  16                 { BITS_EOT }
  17         }},
  18         {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", {
  19                 { BITS_EOT }
  20         }},
  21         {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_HARD_POWERON", "", {
  22                 { BITS_EOT }
  23         }},
  24         {0x2b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_SOFT_POWRON", "", {
  25                 { BITS_EOT }
  26         }},
  27         {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", {
  28                 { BITS_EOT }
  29         }},
  30         {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE", "", {
  31                 { BITS_EOT }
  32         }},
  33         {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", {
  34                 { BITS_EOT }
  35         }},
  36         {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", {
  37                 { BITS_EOT }
  38         }},
  39         {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", {
  40                 { BITS_EOT }
  41         }},
  42         {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", {
  43                 { BITS_EOT }
  44         }},
  45         {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", {
  46                 { BITS_EOT }
  47         }},
  48         {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", {
  49                 { BITS_EOT }
  50         }},
  51         {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", {
  52                 { BITS_EOT }
  53         }},
  54         {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", {
  55                 { BITS_EOT }
  56         }},
  57         {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", {
  58                 { BITS_EOT }
  59         }},
  60         {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", {
  61                 { BITS_EOT }
  62         }},
  63         {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", {
  64                 { BITS_EOT }
  65         }},
  66         {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", {
  67                 { BITS_EOT }
  68         }},
  69         {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", {
  70                 { BITS_EOT }
  71         }},
  72         {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", {
  73                 { BITS_EOT }
  74         }},
  75         {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", {
  76                 { BITS_EOT }
  77         }},
  78         {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", {
  79                 { BITS_EOT }
  80         }},
  81         {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
  82                 { BITS_EOT }
  83         }},
  84         {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
  85                 { BITS_EOT }
  86         }},
  87         {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
  88                 { BITS_EOT }
  89         }},
  90         {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
  91                 { BITS_EOT }
  92         }},
  93         {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
  94                 { BITS_EOT }
  95         }},
  96         {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
  97                 { BITS_EOT }
  98         }},
  99         {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
 100                 { BITS_EOT }
 101         }},
 102         {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
 103                 { BITS_EOT }
 104         }},
 105         {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
 106                 { BITS_EOT }
 107         }},
 108         {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
 109                 { BITS_EOT }
 110         }},
 111         {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
 112                 { BITS_EOT }
 113         }},
 114         {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", {
 115                 { BITS_EOT }
 116         }},
 117         {0x300, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER0", "", {
 118                 { BITS_EOT }
 119         }},
 120         {0x301, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER1", "", {
 121                 { BITS_EOT }
 122         }},
 123         {0x302, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER2", "", {
 124                 { BITS_EOT }
 125         }},
 126         {0x303, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER3", "", {
 127                 { BITS_EOT }
 128         }},
 129         {0x304, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER0", "", {
 130                 { BITS_EOT }
 131         }},
 132         {0x305, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER1", "", {
 133                 { BITS_EOT }
 134         }},
 135         {0x306, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER2", "", {
 136                 { BITS_EOT }
 137         }},
 138         {0x307, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER3", "", {
 139                 { BITS_EOT }
 140         }},
 141         {0x308, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER0", "", {
 142                 { BITS_EOT }
 143         }},
 144         {0x309, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER1", "", {
 145                 { BITS_EOT }
 146         }},
 147         {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER2", "", {
 148                 { BITS_EOT }
 149         }},
 150         {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER3", "", {
 151                 { BITS_EOT }
 152         }},
 153         {0x30c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER0", "", {
 154                 { BITS_EOT }
 155         }},
 156         {0x30d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER1", "", {
 157                 { BITS_EOT }
 158         }},
 159         {0x30e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER2", "", {
 160                 { BITS_EOT }
 161         }},
 162         {0x30f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER3", "", {
 163                 { BITS_EOT }
 164         }},
 165         {0x310, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER4", "", {
 166                 { BITS_EOT }
 167         }},
 168         {0x311, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER5", "", {
 169                 { BITS_EOT }
 170         }},
 171         {0x360, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR0", "", {
 172                 { BITS_EOT }
 173         }},
 174         {0x361, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR1", "", {
 175                 { BITS_EOT }
 176         }},
 177         {0x362, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR2", "", {
 178                 { BITS_EOT }
 179         }},
 180         {0x363, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR3", "", {
 181                 { BITS_EOT }
 182         }},
 183         {0x364, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR0", "", {
 184                 { BITS_EOT }
 185         }},
 186         {0x365, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR1", "", {
 187                 { BITS_EOT }
 188         }},
 189         {0x366, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR2", "", {
 190                 { BITS_EOT }
 191         }},
 192         {0x367, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR3", "", {
 193                 { BITS_EOT }
 194         }},
 195         {0x368, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR0", "", {
 196                 { BITS_EOT }
 197         }},
 198         {0x369, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR1", "", {
 199                 { BITS_EOT }
 200         }},
 201         {0x36a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR2", "", {
 202                 { BITS_EOT }
 203         }},
 204         {0x36b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR3", "", {
 205                 { BITS_EOT }
 206         }},
 207         {0x36c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR0", "", {
 208                 { BITS_EOT }
 209         }},
 210         {0x36d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR1", "", {
 211                 { BITS_EOT }
 212         }},
 213         {0x36e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR2", "", {
 214                 { BITS_EOT }
 215         }},
 216         {0x36f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR3", "", {
 217                 { BITS_EOT }
 218         }},
 219         {0x370, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR4", "", {
 220                 { BITS_EOT }
 221         }},
 222         {0x371, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR5", "", {
 223                 { BITS_EOT }
 224         }},
 225         {0x3a0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR0", "", {
 226                 { BITS_EOT }
 227         }},
 228         {0x3a1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR1", "", {
 229                 { BITS_EOT }
 230         }},
 231         {0x3a2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR0", "", {
 232                 { BITS_EOT }
 233         }},
 234         {0x3a3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR1", "", {
 235                 { BITS_EOT }
 236         }},
 237         {0x3a4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR0", "", {
 238                 { BITS_EOT }
 239         }},
 240         {0x3a5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR1", "", {
 241                 { BITS_EOT }
 242         }},
 243         {0x3a6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR0", "", {
 244                 { BITS_EOT }
 245         }},
 246         {0x3a7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR1", "", {
 247                 { BITS_EOT }
 248         }},
 249         {0x3a8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR0", "", {
 250                 { BITS_EOT }
 251         }},
 252         {0x3a9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR1", "", {
 253                 { BITS_EOT }
 254         }},
 255         {0x3aa, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR0", "", {
 256                 { BITS_EOT }
 257         }},
 258         {0x3ab, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR1", "", {
 259                 { BITS_EOT }
 260         }},
 261         {0x3ac, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR0", "", {
 262                 { BITS_EOT }
 263         }},
 264         {0x3ad, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR1", "", {
 265                 { BITS_EOT }
 266         }},
 267         {0x3ae, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR0", "", {
 268                 { BITS_EOT }
 269         }},
 270         {0x3af, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR1", "", {
 271                 { BITS_EOT }
 272         }},
 273         {0x3b0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR0", "", {
 274                 { BITS_EOT }
 275         }},
 276         {0x3b1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR1", "", {
 277                 { BITS_EOT }
 278         }},
 279         {0x3b2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR0", "", {
 280                 { BITS_EOT }
 281         }},
 282         {0x3b3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", {
 283                 { BITS_EOT }
 284         }},
 285         {0x3b4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IS_ESCR0", "", {
 286                 { BITS_EOT }
 287         }},
 288         {0x3b5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", {
 289                 { BITS_EOT }
 290         }},
 291         {0x3b6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR0", "", {
 292                 { BITS_EOT }
 293         }},
 294         {0x3b7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR1", "", {
 295                 { BITS_EOT }
 296         }},
 297         {0x3b8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR0", "", {
 298                 { BITS_EOT }
 299         }},
 300         {0x3b9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR1", "", {
 301                 { BITS_EOT }
 302         }},
 303         {0x3ba, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR0", "", {
 304                 { BITS_EOT }
 305         }},
 306         {0x3bb, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR1", "", {
 307                 { BITS_EOT }
 308         }},
 309         {0x3bc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR0", "", {
 310                 { BITS_EOT }
 311         }},
 312         {0x3bd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR1", "", {
 313                 { BITS_EOT }
 314         }},
 315         {0x3be, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SSU_ESCR0", "", {
 316                 { BITS_EOT }
 317         }},
 318         {0x3c0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR0", "", {
 319                 { BITS_EOT }
 320         }},
 321         {0x3c1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR1", "", {
 322                 { BITS_EOT }
 323         }},
 324         {0x3c2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR0", "", {
 325                 { BITS_EOT }
 326         }},
 327         {0x3c3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR1", "", {
 328                 { BITS_EOT }
 329         }},
 330         {0x3c4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR0", "", {
 331                 { BITS_EOT }
 332         }},
 333         {0x3c5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR1", "", {
 334                 { BITS_EOT }
 335         }},
 336         {0x3c8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR0", "", {
 337                 { BITS_EOT }
 338         }},
 339         {0x3c9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR1", "", {
 340                 { BITS_EOT }
 341         }},
 342         {0x3ca, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR0", "", {
 343                 { BITS_EOT }
 344         }},
 345         {0x3cb, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR1", "", {
 346                 { BITS_EOT }
 347         }},
 348         {0x3cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR2", "", {
 349                 { BITS_EOT }
 350         }},
 351         {0x3cd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR3", "", {
 352                 { BITS_EOT }
 353         }},
 354         {0x3e0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR4", "", {
 355                 { BITS_EOT }
 356         }},
 357         {0x3e1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR5", "", {
 358                 { BITS_EOT }
 359         }},
 360         {0x3f0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_PRECISE_EVENT", "", {
 361                 { BITS_EOT }
 362         }},
 363         {0x3f1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_ENABLE", "", {
 364                 { BITS_EOT }
 365         }},
 366         {0x3f2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_MATRIX_VERT", "", {
 367                 { BITS_EOT }
 368         }},
 369         {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {
 370                 { BITS_EOT }
 371         }},
 372         {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {
 373                 { BITS_EOT }
 374         }},
 375         {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {
 376                 { BITS_EOT }
 377         }},
 378         {0x403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", {
 379                 { BITS_EOT }
 380         }},
 381         {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", {
 382                 { BITS_EOT }
 383         }},
 384         {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", {
 385                 { BITS_EOT }
 386         }},
 387         {0x406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", {
 388                 { BITS_EOT }
 389         }},
 390         {0x407, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_MISC", "", {
 391                 { BITS_EOT }
 392         }},
 393         {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", {
 394                 { BITS_EOT }
 395         }},
 396         {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", {
 397                 { BITS_EOT }
 398         }},
 399         {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", {
 400                 { BITS_EOT }
 401         }},
 402         {0x40b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_MISC", "", {
 403                 { BITS_EOT }
 404         }},
 405         {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {
 406                 { BITS_EOT }
 407         }},
 408         {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", {
 409                 { BITS_EOT }
 410         }},
 411         {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {
 412                 { BITS_EOT }
 413         }},
 414         {0x40f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_MISC", "", {
 415                 { BITS_EOT }
 416         }},
 417         {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", {
 418                 { BITS_EOT }
 419         }},
 420         {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", {
 421                 { BITS_EOT }
 422         }},
 423         {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", {
 424                 { BITS_EOT }
 425         }},
 426         {0x413, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_MISC", "", {
 427                 { BITS_EOT }
 428         }},
 429         {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", {
 430                 { BITS_EOT }
 431         }},
 432         {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", {
 433                 { BITS_EOT }
 434         }},
 435         {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", {
 436                 { BITS_EOT }
 437         }},
 438         {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", {
 439                 { BITS_EOT }
 440         }},
 441         {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", {
 442                 { BITS_EOT }
 443         }},
 444         {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", {
 445                 { BITS_EOT }
 446         }},
 447         {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", {
 448                 { BITS_EOT }
 449         }},
 450         {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", {
 451                 { BITS_EOT }
 452         }},
 453         {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {
 454                 { BITS_EOT }
 455         }},
 456         {0x17b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CTL", "", {
 457                 { BITS_EOT }
 458         }},
 459         {0x180, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RAX", "", {
 460                 { BITS_EOT }
 461         }},
 462         {0x181, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RBX", "", {
 463                 { BITS_EOT }
 464         }},
 465         {0x182, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RCX", "", {
 466                 { BITS_EOT }
 467         }},
 468         {0x183, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDX", "", {
 469                 { BITS_EOT }
 470         }},
 471         {0x184, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RSI", "", {
 472                 { BITS_EOT }
 473         }},
 474         {0x185, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDI", "", {
 475                 { BITS_EOT }
 476         }},
 477         {0x186, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RBP", "", {
 478                 { BITS_EOT }
 479         }},
 480         {0x187, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RSP", "", {
 481                 { BITS_EOT }
 482         }},
 483         {0x188, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RFLAGS", "", {
 484                 { BITS_EOT }
 485         }},
 486         {0x189, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RIP", "", {
 487                 { BITS_EOT }
 488         }},
 489         {0x18a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_MISC", "", {
 490                 { BITS_EOT }
 491         }},
 492         {0x190, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R8", "", {
 493                 { BITS_EOT }
 494         }},
 495         {0x191, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R9", "", {
 496                 { BITS_EOT }
 497         }},
 498         {0x192, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R10", "", {
 499                 { BITS_EOT }
 500         }},
 501         {0x193, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R11", "", {
 502                 { BITS_EOT }
 503         }},
 504         {0x194, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R12", "", {
 505                 { BITS_EOT }
 506         }},
 507         {0x195, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R13", "", {
 508                 { BITS_EOT }
 509         }},
 510         {0x196, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R14", "", {
 511                 { BITS_EOT }
 512         }},
 513         {0x197, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R15", "", {
 514                 { BITS_EOT }
 515         }},
 516         {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", {
 517                 { BITS_EOT }
 518         }},
 519         {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", {
 520                 { BITS_EOT }
 521         }},
 522         {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE", "", {
 523                 { BITS_EOT }
 524         }},
 525         {0x1d7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_FROM_LIP", "", {
 526                 { BITS_EOT }
 527         }},
 528         {0x1d8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_TO_LIP", "", {
 529                 { BITS_EOT }
 530         }},
 531         {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DEBUGCTLA", "", {
 532                 { BITS_EOT }
 533         }},
 534         {0x1da, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_TOS", "", {
 535                 { BITS_EOT }
 536         }},
 537         {0x1db, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0", "", {
 538                 { BITS_EOT }
 539         }},
 540         {0x1dd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2", "", {
 541                 { BITS_EOT }
 542         }},
 543         {0x1de, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3", "", {
 544                 { BITS_EOT }
 545         }},
 546         {0x277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "", {
 547                 { BITS_EOT }
 548         }},
 549         {0x600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "", {
 550                 { BITS_EOT }
 551         }},
 552         { MSR_EOT }
 553 };