1 ## SPDX-License-Identifier: GPL-2.0-only
3 # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code.
6 default y if HAVE_USBDEBUG_OPTIONS
9 # Use "select HAVE_USBDEBUG_OPTIONS" on southbridges with multiple
10 # EHCI controllers or multiple ports with Debug Port capability
11 config HAVE_USBDEBUG_OPTIONS
15 bool "USB 2.0 EHCI debug dongle support"
17 depends on HAVE_USBDEBUG
19 This option allows you to use a so-called USB EHCI Debug device
20 (such as the Ajays NET20DC, AMIDebug RX, or a system using the
21 Linux "EHCI Debug Device gadget" driver found in recent kernel)
22 to retrieve the coreboot debug messages (instead, or in addition
25 This feature is NOT supported on all chipsets in coreboot!
27 It also requires a USB2 controller which supports the EHCI
28 Debug Port capability.
30 See https://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
31 of supported controllers.
37 config USBDEBUG_IN_PRE_RAM
38 bool "Enable early (pre-RAM) usbdebug"
41 Configuring USB controllers in system-agent binary may cause
42 problems to usbdebug. Disabling this option delays usbdebug to
43 be setup on entry to ramstage.
47 config USBDEBUG_HCD_INDEX
50 prompt "Index for EHCI controller to use with usbdebug" if HAVE_USBDEBUG_OPTIONS
52 Some boards have multiple EHCI controllers with possibly only
53 one having the Debug Port capability on an external USB port.
55 Mapping of this index to PCI device functions is southbridge
56 specific and mainboard level Kconfig should already provide
57 a working default value here.
59 config USBDEBUG_DEFAULT_PORT
62 prompt "Default USB port to use as Debug Port" if HAVE_USBDEBUG_OPTIONS
64 Selects which physical USB port usbdebug dongle is connected to.
65 Setting of 0 means to scan possible ports starting from 1.
67 Intel platforms have hardwired the debug port location and this
68 setting makes no difference there.
70 Hence, if you select the correct port here, you can speed up
71 your boot time. Which USB port number refers to which actual
72 port on your mainboard (potentially also USB pin headers on
73 your mainboard) is highly board-specific, and you'll likely
74 have to find out by trial-and-error.
77 prompt "Type of dongle"
78 default USBDEBUG_DONGLE_STD
80 config USBDEBUG_DONGLE_STD
81 bool "USB gadget driver or Net20DC"
83 Net20DC, BeagleBone Black, Raspberry Pi Zero W
85 config USBDEBUG_DONGLE_BEAGLEBONE
86 bool "BeagleBone (not BeagleBone Black)"
88 Use this to configure the USB hub on BeagleBone board.
89 Do NOT select this for the BeagleBone Black.
91 config USBDEBUG_DONGLE_FTDI_FT232H
92 bool "FTDI FT232H UART"
94 Use this with FT232H usb-to-uart. Configuration is hard-coded
95 to use 8n1, no flow control.
97 config USBDEBUG_DONGLE_WCH_CH347
100 Use this with CH347 usb-to-uart. Configuration is hard-coded
101 to use 8n1, no flow control. For compatibility across modes
102 0, 1, and 3, only UART 1 is supported. The UART in mode 2 is
103 not currently supported.
107 config USBDEBUG_DONGLE_FTDI_FT232H_BAUD
108 int "FTDI FT232H baud rate"
110 depends on USBDEBUG_DONGLE_FTDI_FT232H
112 Select baud rate for FT232H in the range 733..12,000,000. Make
113 sure that your receiving side supports the same setting and your
114 connection works with it. Multiples of 115,200 seem to be a good
115 choice, and EHCI debug usually can't saturate more than 576,000.
117 config USBDEBUG_DONGLE_WCH_CH347_BAUD
118 int "WCH CH347 baud rate"
120 depends on USBDEBUG_DONGLE_WCH_CH347
122 Select baud rate for CH347 in the range 1200..9,000,000. Make
123 sure that your receiving side supports the same setting and your
124 connection works with it. Multiples of 115,200 seem to be a good
125 choice, and EHCI debug usually can't saturate more than 576,000.
127 config USBDEBUG_OPTIONAL_HUB_PORT
129 default 2 if USBDEBUG_DONGLE_BEAGLEBONE