src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/pnp_ops.h>
   4 #include <superio/nuvoton/common/nuvoton.h>
   5 #include <superio/nuvoton/nct6776/nct6776.h>
   6 #include <southbridge/intel/lynxpoint/pch.h>
   7
   8 #define GLOBAL_DEV PNP_DEV(0x2e, 0)
   9 #define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V)
  10 #define GPIO1_ENABLE_DEV PNP_DEV(0x2e, NCT6776_GPIO1234567_V)
  11 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
  12 #define ACPI_DEV   PNP_DEV(0x2e, NCT6776_ACPI)
  13
  14 void mainboard_config_superio(void)
  15 {
  16         nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
  17
  18         /* Select SIO pin mux states */
  19         pnp_write_config(GLOBAL_DEV, 0x1a, 0xf8);
  20         pnp_write_config(GLOBAL_DEV, 0x1b, 0x4e);
  21         pnp_write_config(GLOBAL_DEV, 0x1c, 0x00);
  22         pnp_write_config(GLOBAL_DEV, 0x24, 0x5c);
  23         pnp_write_config(GLOBAL_DEV, 0x27, 0xc0);
  24         pnp_write_config(GLOBAL_DEV, 0x2a, 0x62);
  25         pnp_write_config(GLOBAL_DEV, 0x2b, 0x20);
  26         pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);
  27         pnp_write_config(GLOBAL_DEV, 0x2d, 0x00);
  28         pnp_write_config(GLOBAL_DEV, 0x2f, 0x01);
  29
  30         /* Power on the status LEDs */
  31         pnp_set_logical_device(GPIO1_ENABLE_DEV);
  32         pnp_unset_and_set_config(GPIO1_ENABLE_DEV, 0x30, 0, 1 << 1);
  33
  34         pnp_set_logical_device(GPIO1_DEV);
  35         pnp_write_config(GPIO1_DEV, 0xf0, 0x30);
  36         pnp_write_config(GPIO1_DEV, 0xf1, 0x31);
  37
  38         /* Power RAM in S3 and let the PCH handle power failure actions */
  39         pnp_set_logical_device(ACPI_DEV);
  40         pnp_write_config(ACPI_DEV, 0xe4, 0x70);
  41
  42         nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
  43
  44         /* Enable UART */
  45         nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  46 }