src/mainboard/emulation/qemu-q35/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <device/pci_ops.h>
   6 #include <pc80/keyboard.h>
   7 #include <cpu/x86/smm.h>
   8
   9 #include "q35.h"
  10
  11 static const unsigned char qemu_q35_irqs[] = {
  12         10, 10, 11, 11,
  13         10, 10, 11, 11,
  14 };
  15
  16 static void qemu_nb_init(struct device *dev)
  17 {
  18         /* Map memory at 0xc0000 - 0xfffff */
  19         int i;
  20         uint8_t v = pci_read_config8(dev, D0F0_PAM(0));
  21         v |= 0x30;
  22         pci_write_config8(dev, D0F0_PAM(0), v);
  23         pci_write_config8(dev, D0F0_PAM(1), 0x33);
  24         pci_write_config8(dev, D0F0_PAM(2), 0x33);
  25         pci_write_config8(dev, D0F0_PAM(3), 0x33);
  26         pci_write_config8(dev, D0F0_PAM(4), 0x33);
  27         pci_write_config8(dev, D0F0_PAM(5), 0x33);
  28         pci_write_config8(dev, D0F0_PAM(6), 0x33);
  29
  30         /* This sneaked in here, because Qemu does not emulate a SuperIO chip. */
  31         pc_keyboard_init(NO_AUX_DEVICE);
  32
  33         /* setup IRQ routing for pci slots */
  34         for (i = 0; i < 25; i++) {
  35                 struct device *d = pcidev_on_root(i, 0);
  36                 if (d)
  37                         pci_assign_irqs(d, qemu_q35_irqs + (i % 4));
  38         }
  39         /* setup IRQ routing southbridge devices */
  40         for (i = 25; i < 32; i++) {
  41                 struct device *d = pcidev_on_root(i, 0);
  42                 if (d)
  43                         pci_assign_irqs(d, qemu_q35_irqs);
  44         }
  45 }
  46
  47 static void qemu_nb_read_resources(struct device *dev)
  48 {
  49         size_t tseg_size;
  50         uintptr_t tseg_base;
  51
  52         pci_dev_read_resources(dev);
  53
  54         mmconf_resource(dev, 2);
  55
  56         if (CONFIG(ARCH_RAMSTAGE_X86_64)) {
  57                 /* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */
  58                 reserved_ram_range(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC, 6 * 0x1000);
  59         }
  60
  61         smm_region(&tseg_base, &tseg_size);
  62         reserved_ram_range(dev, ESMRAMC, tseg_base, tseg_size);
  63 }
  64
  65
  66 struct device_operations nb_operations = {
  67         .read_resources   = qemu_nb_read_resources,
  68         .set_resources    = pci_dev_set_resources,
  69         .enable_resources = pci_dev_enable_resources,
  70         .init             = qemu_nb_init,
  71 };