src/mainboard/google/brya/variants/aurash/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A14 : USB_OC1# ==> NC */
  11         PAD_NC(GPP_A14, NONE),
  12         /* A19 : DDSP_HPD1 ==> NC */
  13         PAD_NC(GPP_A19, NONE),
  14         /* A20 : DDSP_HPD2 ==> DDIC_DP_HPD4 */
  15         PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
  16         /* A21 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */
  17         PAD_CFG_GPO(GPP_A21, 1, DEEP),
  18         /* A22 : DDPC_CTRLDATA ==> NC */
  19         PAD_NC(GPP_A22, NONE),
  20
  21         /* B2  : VRALERT# ==> NC */
  22         PAD_NC(GPP_B2, NONE),
  23         /* B3  : PROC_GP2 ==> EMMC_PERST_L */
  24         PAD_CFG_GPO(GPP_B3, 1, DEEP),
  25
  26         /* D6  : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */
  27         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
  28         /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */
  29         PAD_CFG_GPO(GPP_D14, 1, DEEP),
  30
  31         /* E1  : THC0_SPI1_IO2 ==> B2B_HDMICARD_DETN */
  32         PAD_CFG_GPI(GPP_E1, NONE, DEEP),
  33         /* E2  : THC0_SPI1_IO3 ==> B2B_DPCARD_DETN */
  34         PAD_CFG_GPI(GPP_E2, NONE, DEEP),
  35         /* E20 : DDP2_CTRLCLK ==> DDIC_DP_CTRCLK */
  36         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
  37         /* E21 : DDP2_CTRLDATA ==> DDIC_DP_CTRLDATA */
  38         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
  39
  40         /* H19 : SRCCLKREQ4# ==> LAN_I225V_CLKREQ_ODL */
  41         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
  42
  43         /* R6 : I2S2_TXD ==> NC */
  44         PAD_NC(GPP_R6, NONE),
  45         /* R7 : I2S2_RXD ==> NC */
  46         PAD_NC(GPP_R7, NONE),
  47
  48         /* GPD11: LANPHYC ==> LAN_DISABLE_N */
  49         PAD_CFG_GPO(GPD11, 0, DEEP),
  50 };
  51
  52
  53 /* Early pad configuration in bootblock */
  54 static const struct pad_config early_gpio_table[] = {
  55         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  56         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  57         /* A21 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */
  58         PAD_CFG_GPO(GPP_A21, 1, DEEP),
  59         /* B3  : PROC_GP2 ==> EMMC_PERST_L */
  60         PAD_CFG_GPO(GPP_B3, 0, DEEP),
  61         /* B4  : PROC_GP3 ==> SSD_PERST_L */
  62         PAD_CFG_GPO(GPP_B4, 0, DEEP),
  63         /*
  64          * D1  : ISH_GP1 ==> FP_RST_ODL
  65          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
  66          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
  67          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
  68          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
  69          * FPMCU not working after a S3 resume. This is a known issue.
  70          */
  71         PAD_CFG_GPO(GPP_D1, 0, DEEP),
  72         /* D2  : ISH_GP2 ==> EN_FP_PWR */
  73         PAD_CFG_GPO(GPP_D2, 1, DEEP),
  74         /* D18 : UART1_TXD ==> SD_PE_RST_L */
  75         PAD_CFG_GPO(GPP_D18, 0, PLTRST),
  76         /* E15 : RSVD_TP ==> PCH_WP_OD */
  77         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
  78         /* F14 : GSXDIN ==> EN_PP3300_SSD */
  79         PAD_CFG_GPO(GPP_F14, 1, DEEP),
  80         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
  81         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
  82         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
  83         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
  84         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
  85         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
  86         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
  87         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
  88         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
  89         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
  90         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
  91         PAD_CFG_GPO(GPP_H13, 1, DEEP),
  92
  93         /* CPU PCIe VGPIO for PEG60 */
  94         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
  95         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
  96         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
  97         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
  98         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
  99         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 100         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 101         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 102         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 103         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 104         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 105         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 106         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 107         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 108         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 109         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 110         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 111         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 112         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 113         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 114 };
 115 static const struct pad_config romstage_gpio_table[] = {
 116         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 117         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 118         /* D18 : UART1_TXD ==> SD_PE_RST_L */
 119         PAD_CFG_GPO(GPP_D18, 1, DEEP),
 120 };
 121
 122 const struct pad_config *variant_gpio_override_table(size_t *num)
 123 {
 124         *num = ARRAY_SIZE(override_gpio_table);
 125         return override_gpio_table;
 126 }
 127
 128 const struct pad_config *variant_early_gpio_table(size_t *num)
 129 {
 130         *num = ARRAY_SIZE(early_gpio_table);
 131         return early_gpio_table;
 132 }
 133
 134 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 135 {
 136         *num = ARRAY_SIZE(romstage_gpio_table);
 137         return romstage_gpio_table;
 138 }