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mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support
[coreboot.git] / src / mainboard / google / brya / variants / aurash / overridetree.cb
bloba18197627c88838ea7de228ed7c59873238626fb
1 fw_config
2 field USBC0_RETIMER 2 3
3 option USBC0_RETIMER_ABSENT 0
4 option USBC0_RETIMER_PRESENT 1
5 end
6 field STORAGE 4 5
7 option STORAGE_UNKNOWN 0
8 option STORAGE_NVME 1
9 option STORAGE_EMMC 2
10 end
11 field AUDIO 6
12 option AUDIO_UNKNOWN 0
13 option NAU88L25B_I2S 1
14 end
15 end
16 chip soc/intel/alderlake
17 # As per Intel Advisory doc#723158, the change is required to prevent possible
18 # display flickering issue.
19 register "usb2_phy_sus_pg_disable" = "1"
20 # Enable HDMI2 in PortA, HDMI1 in PortB, HDMI/DP in Port2
21 register "ddi_ports_config" = "{
22 [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
23 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
24 [DDI_PORT_1] = DDI_ENABLE_HPD,
25 [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
26 [DDI_PORT_3] = DDI_ENABLE_HPD,
27 }"
28 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port2
29 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2 Port3
30 register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # Enable USB2 Port4
31 register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port9
32 register "usb3_ports[2]" = "{
33 .enable = 1,
34 .ocpin = OC_SKIP,
35 .tx_de_emp = 0x2B,
36 .tx_downscale_amp = 0x00,
37 }" # Type-A port A2
38 register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3
39 # Bitmap for Wake Enable on USB attach/detach
40 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(4) |
41 USB_PORT_WAKE_ENABLE(6) |
42 USB_PORT_WAKE_ENABLE(7) |
43 USB_PORT_WAKE_ENABLE(8)"
44 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
45 USB_PORT_WAKE_ENABLE(2) |
46 USB_PORT_WAKE_ENABLE(3) |
47 USB_PORT_WAKE_ENABLE(4)"
48 register "tcc_offset" = "0" # TCC of 100C
49 register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
50 .tdp_pl1_override = 15,
51 .tdp_pl2_override = 25,
52 }"
53 register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
54 .tdp_pl1_override = 64,
55 }"
56 device domain 0 on
57 device ref dtt on
58 chip drivers/intel/dptf
59 ## sensor information
60 register "options.tsr[0].desc" = ""SSD""
61 register "options.tsr[1].desc" = ""CPU_VR""
62 register "options.tsr[2].desc" = ""DIMM""
63
64
65 ## Passive Policy
66 register "policies.passive" = "{
67 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
68 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
69 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
70 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
71 }"
72
73 ## Critical Policy
74 register "policies.critical" = "{
75 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
76 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
77 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
78 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
79 }"
80
81 register "controls.power_limits" = "{
82 .pl1 = {
83 .min_power = 15000,
84 .max_power = 55000,
85 .time_window_min = 28 * MSECS_PER_SEC,
86 .time_window_max = 32 * MSECS_PER_SEC,
87 .granularity = 200,
88 },
89 .pl2 = {
90 .min_power = 55000,
91 .max_power = 55000,
92 .time_window_min = 28 * MSECS_PER_SEC,
93 .time_window_max = 32 * MSECS_PER_SEC,
94 .granularity = 1000,
95 }
96 }"
97
98 register "oem_data.oem_variables" = "{
99 [0] = 0x1
100 }"
101
102 device generic 0 alias dptf_policy on end
103 end
104 end
105 device ref tcss_dma0 on
106 chip drivers/intel/usb4/retimer
107 register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
108 use tcss_usb3_port1 as dfp[0].typec_port
109 device generic 0 on end
110 end
111 end
112 device ref tcss_dma1 on
113 chip drivers/intel/usb4/retimer
114 register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
115 use tcss_usb3_port3 as dfp[0].typec_port
116 device generic 0 on end
117 end
118 end # USB4 Port
119 device ref pcie4_0 on
120 # Enable CPU PCIE RP 1 using CLK 0
121 register "cpu_pcie_rp[CPU_RP(1)]" = "{
122 .clk_req = 0,
123 .clk_src = 0,
124 .flags = PCIE_RP_LTR | PCIE_RP_AER,
125 }"
126 probe STORAGE STORAGE_NVME
127 probe STORAGE STORAGE_UNKNOWN
128 end # SSD
129 device ref cnvi_wifi on
130 chip drivers/wifi/generic
131 register "wake" = "GPE0_PME_B0"
132 device generic 0 on end
133 end
134 end # WiFi
135 device ref i2c0 on
136 chip drivers/i2c/nau8825
137 register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
138 register "jkdet_enable" = "1"
139 register "jkdet_pull_enable" = "0"
140 register "jkdet_pull_up" = "0"
141 register "jkdet_polarity" = "1" # ActiveLow
142 register "vref_impedance" = "2" # 125kOhm
143 register "micbias_voltage" = "6" # 2.754
144 register "sar_threshold_num" = "4"
145 register "sar_threshold[0]" = "0x0C"
146 register "sar_threshold[1]" = "0x1C"
147 register "sar_threshold[2]" = "0x38"
148 register "sar_threshold[3]" = "0x60"
149 register "sar_hysteresis" = "1"
150 register "sar_voltage" = "0" # VDDA
151 register "sar_compare_time" = "0" # 500ns
152 register "sar_sampling_time" = "0" # 2us
153 register "short_key_debounce" = "2" # 100ms
154 register "jack_insert_debounce" = "7" # 512ms
155 register "jack_eject_debounce" = "7" # 512ms
156 device i2c 1a on end
157 end
158 end # Audio Nau8825
159 device ref pcie_rp6 on
160 # Enable PCIe-to-i225 bridge PCIe 6 using clk 4
161 register "pch_pcie_rp[PCH_RP(6)]" = "{
162 .clk_src = 4,
163 .clk_req = 4,
164 .flags = PCIE_RP_LTR | PCIE_RP_AER,
165 }"
166 device pci 00.0 on end
167 end # IntelI225V Ethernet NIC
168 device ref pcie_rp7 on
169 chip drivers/net
170 register "customized_leds" = "0x0482"
171 register "wake" = "GPE0_DW0_07"
172 register "device_index" = "0"
173 register "add_acpi_dma_property" = "true"
174 device pci 00.0 on end
175 end
176 end # RTL8111K Ethernet NIC
177 device ref pcie_rp8 off end #pcie_rp 8 Empty
178 device ref pcie_rp9 off end #pcie_rp 9 Empty
179 device ref pcie_rp10 off end #pcie_rp 10 Empty
180 device ref pcie_rp11 off end #pcie_rp 11 Empty
181 device ref pcie_rp12 on
182 chip soc/intel/common/block/pcie/rtd3
183 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21)"
184 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
185 register "srcclk_pin" = "1"
186 register "reset_delay_ms" = "50"
187 register "enable_delay_ms" = "20"
188 device generic 0 on
189 probe STORAGE STORAGE_EMMC
190 probe STORAGE STORAGE_UNKNOWN
191 end
192 end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1
193 register "pch_pcie_rp[PCH_RP(12)]" = "{
194 .clk_src = 1,
195 .clk_req = 1,
196 .flags = PCIE_RP_LTR | PCIE_RP_AER,
197 }"
198 probe STORAGE STORAGE_EMMC
199 probe STORAGE STORAGE_UNKNOWN
200 end # BH799BB
201 device ref pch_espi on
202 chip ec/google/chromeec
203 use conn0 as mux_conn[0]
204 use conn1 as mux_conn[1]
205 device pnp 0c09.0 on end
206 end
207 end
208 device ref pmc hidden
209 chip drivers/intel/pmc_mux
210 device generic 0 on
211 chip drivers/intel/pmc_mux/conn
212 use usb2_port1 as usb2_port
213 use tcss_usb3_port1 as usb3_port
214 device generic 0 alias conn0 on end
215 end
216 chip drivers/intel/pmc_mux/conn
217 use usb2_port3 as usb2_port
218 use tcss_usb3_port3 as usb3_port
219 device generic 1 alias conn1 on end
220 end
221 end
222 end
223 end
224 device ref tcss_xhci on
225 chip drivers/usb/acpi
226 device ref tcss_root_hub on
227 chip drivers/usb/acpi
228 register "desc" = ""USB3 Type-C Port C0 (MLB)""
229 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
230 register "use_custom_pld" = "true"
231 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
232 device ref tcss_usb3_port1 on end
233 end
234 chip drivers/usb/acpi
235 register "desc" = ""USB3 Type-C Port C2 (MLB)""
236 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
237 register "use_custom_pld" = "true"
238 register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
239 device ref tcss_usb3_port3 on end
240 end
241 end
242 end
243 end
244 device ref xhci on
245 chip drivers/usb/acpi
246 device ref xhci_root_hub on
247 chip drivers/usb/acpi
248 register "desc" = ""USB2 Type-C Port C0 (MLB)""
249 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
250 register "use_custom_pld" = "true"
251 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
252 device ref usb2_port1 on end
253 end
254 chip drivers/usb/acpi
255 register "desc" = ""USB2 Type-C Port C2 (MLB)""
256 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
257 register "use_custom_pld" = "true"
258 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
259 device ref usb2_port3 on end
260 end
261 chip drivers/usb/acpi
262 register "desc" = ""USB2 Type-A Port A4 (MLB)""
263 register "type" = "UPC_TYPE_A"
264 register "use_custom_pld" = "true"
265 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
266 device ref usb2_port4 on end
267 end
268 chip drivers/usb/acpi
269 register "desc" = ""USB2 NFC""
270 register "type" = "UPC_TYPE_INTERNAL"
271 device ref usb2_port5 on end
272 end
273 chip drivers/usb/acpi
274 register "desc" = ""USB2 Type-A Port A3 (MLB)""
275 register "type" = "UPC_TYPE_A"
276 register "use_custom_pld" = "true"
277 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
278 device ref usb2_port6 on end
279 end
280 chip drivers/usb/acpi
281 register "desc" = ""USB2 Type-A Port A2 (MLB)""
282 register "type" = "UPC_TYPE_A"
283 register "use_custom_pld" = "true"
284 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
285 device ref usb2_port7 on end
286 end
287 chip drivers/usb/acpi
288 register "desc" = ""USB2 Type-A Port A1 (MLB)""
289 register "type" = "UPC_TYPE_A"
290 register "use_custom_pld" = "true"
291 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 1))"
292 device ref usb2_port8 on end
293 end
294 chip drivers/usb/acpi
295 register "desc" = ""USB2 Bluetooth""
296 register "type" = "UPC_TYPE_INTERNAL"
297 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
298 device ref usb2_port10 on end
299 end
300 chip drivers/usb/acpi
301 register "desc" = ""USB3 Type-A Port A1 (MLB)""
302 register "type" = "UPC_TYPE_USB3_A"
303 register "use_custom_pld" = "true"
304 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 2))"
305 device ref usb3_port1 on end
306 end
307 chip drivers/usb/acpi
308 register "desc" = ""USB3 Type-A Port A2 (MLB)""
309 register "type" = "UPC_TYPE_USB3_A"
310 register "use_custom_pld" = "true"
311 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
312 device ref usb3_port2 on end
313 end
314 chip drivers/usb/acpi
315 register "desc" = ""USB3 Type-A Port A3 (MLB)""
316 register "type" = "UPC_TYPE_USB3_A"
317 register "use_custom_pld" = "true"
318 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
319 device ref usb3_port3 on end
320 end
321 chip drivers/usb/acpi
322 register "desc" = ""USB3 Type-A Port A4 (MLB)""
323 register "type" = "UPC_TYPE_USB3_A"
324 register "use_custom_pld" = "true"
325 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
326 device ref usb3_port4 on end
327 end
328 end
329 end
330 end # USB2 and USB3 Port
331 end
332
333 end
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