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mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support
[coreboot.git] / src / mainboard / google / brya / variants / bujia / overridetree.cb
blob6db60acb67e64cefc09a061481e32fe32c9115a1
1 chip soc/intel/alderlake
2 register "sagv" = "SaGv_Enabled"
3
4 # Intel Common SoC Config
5 #+-------------------+---------------------------+
6 #| Field | Value |
7 #+-------------------+---------------------------+
8 #| GSPI1 | NC |
9 #| I2C0 | Audio |
10 #| I2C1 | cr50 TPM. Early init is |
11 #| | required to set up a BAR |
12 #| | for TPM communication |
13 #| I2C3 | NC |
14 #| I2C5 | NC |
15 #+-------------------+---------------------------+
16 register "common_soc_config" = "{
17 .i2c[0] = {
18 .speed = I2C_SPEED_FAST,
19 .rise_time_ns = 600,
20 .fall_time_ns = 400,
21 .data_hold_time_ns = 50,
22 },
23 .i2c[1] = {
24 .early_init = 1,
25 .speed = I2C_SPEED_FAST,
26 .rise_time_ns = 600,
27 .fall_time_ns = 400,
28 .data_hold_time_ns = 50,
29 },
30 }"
31
32 register "usb2_ports[0]" = "USB2_PORT_MAX_TYPE_C(OC2)" # set to Max for USB2_C0
33 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2
34 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3
35 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Port 3 - Port 5 for OPS interface
36 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable Port 6
37
38 register "usb3_ports[2]" = "USB3_PORT_EMPTY " # Disable Port 2
39 # USB3 Port 3 for OPS interface
40
41 register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable Port1
42 register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2
43
44 register "serial_io_gspi_mode" = "{
45 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
46 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
47 }"
48
49 register "serial_io_uart_mode" = "{
50 [PchSerialIoIndexUART0] = PchSerialIoPci,
51 [PchSerialIoIndexUART1] = PchSerialIoPci,
52 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
53 }"
54
55 register "ddi_ports_config" = "{
56 [DDI_PORT_A] = DDI_ENABLE_HPD,
57 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
58 [DDI_PORT_1] = DDI_ENABLE_HPD,
59 [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
60 }"
61
62 device domain 0 on
63 device ref dtt on
64 chip drivers/intel/dptf
65 ## sensor information
66 register "options.tsr[0].desc" = ""DRAM""
67 register "options.tsr[1].desc" = ""Charger""
68 register "options.tsr[2].desc" = ""Wireless""
69 register "options.tsr[3].desc" = ""Memory""
70
71 ## Passive Policy
72 register "policies.passive" = "{
73 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
74 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
75 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
76 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
77 [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000),
78 }"
79
80 ## Critical Policy
81 register "policies.critical" = "{
82 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
83 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
84 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
85 }"
86
87 register "controls.power_limits" = "{
88 .pl1 = {
89 .min_power = 3000,
90 .max_power = 15000,
91 .time_window_min = 28 * MSECS_PER_SEC,
92 .time_window_max = 32 * MSECS_PER_SEC,
93 .granularity = 200,
94 },
95 .pl2 = {
96 .min_power = 55000,
97 .max_power = 55000,
98 .time_window_min = 28 * MSECS_PER_SEC,
99 .time_window_max = 32 * MSECS_PER_SEC,
100 .granularity = 1000,
101 }
102 }"
103
104 ## Charger Performance Control (Control, mA)
105 register "controls.charger_perf" = "{
106 [0] = { 255, 1700 },
107 [1] = { 24, 1500 },
108 [2] = { 16, 1000 },
109 [3] = { 8, 500 }
110 }"
111
112 device generic 0 alias dptf_policy on end
113 end
114 end
115 device ref pcie4_0 on
116 # Enable CPU PCIE RP 1 using CLK 0
117 register "cpu_pcie_rp[CPU_RP(1)]" = "{
118 .clk_req = 0,
119 .clk_src = 0,
120 .flags = PCIE_RP_LTR | PCIE_RP_AER,
121 }"
122 end #NVME
123 device ref tbt_pcie_rp0 off end
124 device ref tbt_pcie_rp1 off end
125 device ref tbt_pcie_rp2 off end
126
127 device ref tcss_dma0 off end
128 device ref tcss_dma1 off end
129 device ref cnvi_wifi on
130 chip drivers/wifi/generic
131 register "wake" = "GPE0_PME_B0"
132 device generic 0 on end
133 end
134 end
135 device ref i2c0 on
136 chip drivers/i2c/generic
137 register "hid" = ""RTL5682""
138 register "name" = ""RT58""
139 register "desc" = ""Headset Codec""
140 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
141 # Set the jd_src to RT5668_JD1 for jack detection
142 register "property_count" = "1"
143 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
144 register "property_list[0].name" = ""realtek,jd-src""
145 register "property_list[0].integer" = "1"
146 device i2c 1a on end
147 end
148 end # I2C0
149 device ref i2c1 on
150 chip drivers/i2c/tpm
151 register "hid" = ""GOOG0005""
152 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
153 device i2c 50 on end
154 end
155 end # I2C1
156 device ref pcie_rp7 on
157 chip drivers/net
158 register "wake" = "GPE0_DW0_07"
159 register "customized_leds" = "0x060f"
160 register "enable_aspm_l1_2" = "1"
161 register "add_acpi_dma_property" = "true"
162 device pci 00.0 on end
163 end
164 end # RTL8111 Ethernet NIC
165 device ref pcie_rp8 off end # disable SD reader
166 device ref gspi1 off end
167 device ref pch_espi on
168 chip ec/google/chromeec
169 use conn0 as mux_conn[0]
170 device pnp 0c09.0 on end
171 end
172 end
173 device ref pmc hidden
174 chip drivers/intel/pmc_mux
175 device generic 0 on
176 chip drivers/intel/pmc_mux/conn
177 use usb2_port1 as usb2_port
178 use tcss_usb3_port1 as usb3_port
179 device generic 0 alias conn0 on end
180 end
181 end
182 end
183 end
184 device ref tcss_xhci on
185 chip drivers/usb/acpi
186 device ref tcss_root_hub on
187 chip drivers/usb/acpi
188 register "desc" = ""USB3 Type-C Port C0 (MLB)""
189 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
190 register "use_custom_pld" = "true"
191 register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 1))"
192 device ref tcss_usb3_port1 on end
193 end
194 end
195 end
196 end
197 device ref xhci on
198 chip drivers/usb/acpi
199 device ref xhci_root_hub on
200 chip drivers/usb/acpi
201 register "desc" = ""USB2 Type-C Port C0 (MLB)""
202 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
203 register "use_custom_pld" = "true"
204 register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 1))"
205 device ref usb2_port1 on end
206 end
207 chip drivers/usb/acpi
208 register "desc" = ""USB2 Type-A Port A3 (MLB)""
209 register "type" = "UPC_TYPE_A"
210 register "use_custom_pld" = "true"
211 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))"
212 register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
213 device ref usb2_port2 on end
214 end
215 chip drivers/usb/acpi
216 register "desc" = ""USB2 Type-A Port A2 (MLB)""
217 register "type" = "UPC_TYPE_A"
218 register "use_custom_pld" = "true"
219 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(3, 1))"
220 register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
221 device ref usb2_port3 on end
222 end
223 chip drivers/usb/acpi
224 register "desc" = ""USB2 OPS interface TX25A""
225 register "type" = "UPC_TYPE_A"
226 register "use_custom_pld" = "true"
227 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))"
228 device ref usb2_port4 on end
229 end
230 chip drivers/usb/acpi
231 register "desc" = ""USB2 OPS interface TX25A""
232 register "type" = "UPC_TYPE_A"
233 register "use_custom_pld" = "true"
234 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
235 device ref usb2_port5 on end
236 end
237 chip drivers/usb/acpi
238 register "desc" = ""USB2 OPS interface TX25A""
239 register "type" = "UPC_TYPE_A"
240 register "use_custom_pld" = "true"
241 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
242 device ref usb2_port6 on end
243 end
244 chip drivers/usb/acpi
245 register "desc" = ""USB2 Type-A Port A1 (MLB)""
246 register "type" = "UPC_TYPE_A"
247 register "use_custom_pld" = "true"
248 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(7, 1))"
249 register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
250 device ref usb2_port8 on end
251 end
252 chip drivers/usb/acpi
253 register "desc" = ""USB2 Type-A Port A0 (MLB)""
254 register "type" = "UPC_TYPE_A"
255 register "use_custom_pld" = "true"
256 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(8, 1))"
257 register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
258 device ref usb2_port9 on end
259 end
260 chip drivers/usb/acpi
261 register "desc" = ""USB2 Bluetooth""
262 register "type" = "UPC_TYPE_INTERNAL"
263 register "reset_gpio" =
264 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
265 device ref usb2_port10 on end
266 end
267 chip drivers/usb/acpi
268 register "desc" = ""USB3 Type-A Port A0 (MLB)""
269 register "type" = "UPC_TYPE_USB3_A"
270 register "use_custom_pld" = "true"
271 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(8, 1))"
272 register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
273 device ref usb3_port1 on end
274 end
275 chip drivers/usb/acpi
276 register "desc" = ""USB3 Type-A Port A1 (MLB)""
277 register "type" = "UPC_TYPE_USB3_A"
278 register "use_custom_pld" = "true"
279 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(7, 1))"
280 register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
281 device ref usb3_port2 on end
282 end
283 chip drivers/usb/acpi
284 register "desc" = ""USB3 OPS interface TX25A""
285 register "type" = "UPC_TYPE_USB3_A"
286 register "use_custom_pld" = "true"
287 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))"
288 device ref usb3_port4 on end
289 end
290 end
291 end
292 end
293 end
294 end
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