src/mainboard/google/brya/variants/crota/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <gpio.h>
   6
   7 static const struct mb_cfg baseboard_memcfg = {
   8         .type = MEM_TYPE_LP5X,
   9
  10         .rcomp = {
  11                 /* Baseboard uses only 100ohm Rcomp resistors */
  12                 .resistor = 100,
  13
  14                 /* Baseboard Rcomp target values */
  15                 .targets = { 40, 36, 35, 35, 35 },
  16         },
  17
  18         /* DQ byte map */
  19         .lpx_dq_map = {
  20                 .ddr0 = {
  21                         .dq0 = {  0,  3,  1,  2,  7, 6,  4, 5, },
  22                         .dq1 = { 13, 12, 14, 15, 11, 8, 10, 9, },
  23                 },
  24                 .ddr1 = {
  25                         .dq0 = { 7, 6,  5,  4,  2,  1,  0,  3, },
  26                         .dq1 = { 9, 8, 10, 11, 13, 14, 15, 12, },
  27                 },
  28                 .ddr2 = {
  29                         .dq0 = { 8, 11, 9, 10, 12, 14, 13, 15, },
  30                         .dq1 = { 5,  7, 6,  4,  1,  2,  3,  0, },
  31                 },
  32                 .ddr3 = {
  33                         .dq0 = {  2,  0,  1,  3,  7, 6, 5,  4, },
  34                         .dq1 = { 12, 13, 14, 15, 11, 8, 9, 10, },
  35                 },
  36                 .ddr4 = {
  37                         .dq0 = {  0,  3,  1,  2,  7, 5,  6, 4, },
  38                         .dq1 = { 12, 14, 13, 15, 10, 8, 11, 9, },
  39                 },
  40                 .ddr5 = {
  41                         .dq0 = { 10, 8, 9, 11, 13, 15, 14, 12, },
  42                         .dq1 = {  7, 6, 5,  4,  3,  1,  0,  2, },
  43                 },
  44                 .ddr6 = {
  45                         .dq0 = { 6, 4,  5,  7,  1,  0,  2,  3, },
  46                         .dq1 = { 8, 9, 10, 11, 13, 15, 14, 12, },
  47                 },
  48                 .ddr7 = {
  49                         .dq0 = {  1,  2,  0,  3,  5, 6,  7, 4, },
  50                         .dq1 = { 12, 13, 14, 15, 11, 8, 10, 9, },
  51                 },
  52         },
  53
  54         /* DQS CPU<>DRAM map */
  55         .lpx_dqs_map = {
  56                 .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
  57                 .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
  58                 .ddr2 = { .dqs0 = 1, .dqs1 = 0 },
  59                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
  60                 .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
  61                 .ddr5 = { .dqs0 = 1, .dqs1 = 0 },
  62                 .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
  63                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 }
  64         },
  65
  66         .lp5x_config = {
  67                 .ccc_config = 0xff,
  68         },
  69
  70         .LpDdrDqDqsReTraining = 1,
  71
  72         .ect = 1, /* Early Command Training */
  73
  74 };
  75
  76 const struct mb_cfg *variant_memory_params(void)
  77 {
  78         return &baseboard_memcfg;
  79 }
  80
  81 int variant_memory_sku(void)
  82 {
  83         /*
  84          * Memory configuration board straps
  85          * GPIO_MEM_CONFIG_0    GPP_E11
  86          * GPIO_MEM_CONFIG_1    GPP_E2
  87          * GPIO_MEM_CONFIG_2    GPP_E1
  88          * GPIO_MEM_CONFIG_3    GPP_E12
  89          */
  90         gpio_t spd_gpios[] = {
  91                 GPP_E11,
  92                 GPP_E2,
  93                 GPP_E1,
  94                 GPP_E12,
  95         };
  96
  97         return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
  98 }
  99
 100 bool variant_is_half_populated(void)
 101 {
 102         /* GPIO_MEM_CH_SEL GPP_E13 */
 103         return gpio_get(GPP_E13);
 104 }