src/mainboard/google/brya/variants/gaelin/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  11         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  12         /* A17 : DISP_MISCC ==> EN_FCAM_PWR */
  13         PAD_CFG_GPO(GPP_A17, 1, DEEP),
  14         /* A19 : DDSP_HPD1 ==> NC */
  15         PAD_NC(GPP_A19, NONE),
  16         /* A20 : DDSP_HPD2 ==> NC */
  17         PAD_NC(GPP_A20, NONE),
  18         /* A21 : DDPC_CTRCLK ==> NC */
  19         PAD_NC(GPP_A21, NONE),
  20         /* A22 : DDPC_CTRLDATA ==> NC */
  21         PAD_NC(GPP_A22, NONE),
  22
  23         /* B2  : VRALERT# ==> NC */
  24         PAD_NC(GPP_B2, NONE),
  25         /* B3  : PROC_GP2 ==> NC */
  26         PAD_NC(GPP_B3, NONE),
  27         /* B4  : PROC_GP3 ==> SSD_PERST_L */
  28         PAD_CFG_GPO(GPP_B4, 1, DEEP),
  29         /* B7  : ISH_I2C1_SDA ==> I2C_TCHSCR_SDA */
  30         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
  31         /* B8  : ISH_I2C1_SCL ==> I2C_TCHSCR_SCL */
  32         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
  33
  34         /* C6  : SML1CLK ==> USI_EN_PWR */
  35         PAD_CFG_GPO(GPP_C6, 1, DEEP),
  36         /* C7  : SML1DATA ==> USI_INT_L */
  37         PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE),
  38
  39         /* D0  : ISH_GP0 ==> NC */
  40         PAD_NC(GPP_D0, NONE),
  41         /* D1  : ISH_GP1 ==> NC */
  42         PAD_NC(GPP_D1, NONE),
  43         /* D2  : ISH_GP2 ==> NC */
  44         PAD_NC(GPP_D2, NONE),
  45         /* D3  : ISH_GP3 ==> NC */
  46         PAD_NC(GPP_D3, NONE),
  47         /* D8  : SRCCLKREQ3# ==> NC */
  48         PAD_NC(GPP_D8, NONE),
  49         /* D9  : ISH_SPI_CS# ==> NC */
  50         PAD_NC(GPP_D9, NONE),
  51         /* D11 : ISH_SPI_MISO ==> NC */
  52         PAD_NC(GPP_D11, NONE),
  53         /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
  54         PAD_NC(GPP_D12, NONE),
  55         /* D17 : UART1_RXD ==> NC */
  56         PAD_NC(GPP_D17, NONE),
  57         /* D18 : UART1_TXD ==> NC */
  58         PAD_NC(GPP_D18, NONE),
  59
  60         /* E4  : SATA_DEVSLP0 ==> USB_A0_RT_RST_ODL */
  61         PAD_CFG_GPO(GPP_E4, 1, DEEP),
  62         /* E5  : SATA_DEVSLP1 ==> USB_A1_RT_RST_ODL */
  63         PAD_CFG_GPO(GPP_E5, 1, DEEP),
  64         /* E7  : PROC_GP1 ==> EN_MIC_PWR */
  65         PAD_CFG_GPO(GPP_E7, 1, DEEP),
  66         /* E14 : DDSP_HPDA ==> EDP_HPD */
  67         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
  68         /* E15 : RSVD_TP ==> PCH_WP_OD */
  69         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
  70         /* E18 : DDP1_CTRLCLK ==> NC */
  71         PAD_NC(GPP_E18, NONE),
  72         /* E20 : DDP2_CTRLCLK ==> NC */
  73         PAD_NC(GPP_E20, NONE),
  74
  75         /* F11 : THC1_SPI2_CLK ==> NC */
  76         PAD_NC(GPP_F11, NONE),
  77         /* F12 : GSXDOUT ==> NC */
  78         PAD_NC(GPP_F12, NONE),
  79         /* F13 : GSXDOUT ==> NC */
  80         PAD_NC(GPP_F13, NONE),
  81         /* F14 : GSXDIN ==> EN_PP3300_SSD */
  82         PAD_CFG_GPO(GPP_F14, 1, DEEP),
  83         /* F15 : GSXSRESET# ==> NC */
  84         PAD_NC(GPP_F15, NONE),
  85         /* F16 : GSXCLK ==> NC */
  86         PAD_NC(GPP_F16, NONE),
  87         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
  88         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
  89
  90         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
  91         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
  92         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
  93         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
  94         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
  95         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
  96         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
  97         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
  98         /* H12 : I2C7_SDA ==> NC */
  99         PAD_NC(GPP_H12, NONE),
 100         /* H13 : I2C7_SCL ==> NC */
 101         PAD_NC(GPP_H13, NONE),
 102
 103         /* R6 : I2S2_TXD ==> NC */
 104         PAD_NC(GPP_R6, NONE),
 105         /* R7 : I2S2_RXD ==> NC */
 106         PAD_NC(GPP_R7, NONE),
 107
 108         /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */
 109         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
 110         /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */
 111         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
 112         /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */
 113         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
 114         /* S6 : SNDW3_CLK ==> DMIC_CLK1_R */
 115         PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
 116         /* S7 : SNDW3_DATA ==> DMIC_DATA1_R */
 117         PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
 118 };
 119
 120 /* Early pad configuration in bootblock */
 121 static const struct pad_config early_gpio_table[] = {
 122         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 123         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 124         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 125         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 126         /* E15 : RSVD_TP ==> PCH_WP_OD */
 127         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 128         /* F14 : GSXDIN ==> EN_PP3300_SSD */
 129         PAD_CFG_GPO(GPP_F14, 1, DEEP),
 130         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 131         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 132         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 133         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 134         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 135         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 136         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 137         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 138         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 139         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 140
 141         /* CPU PCIe VGPIO for PEG60 */
 142         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 143         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 144         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 145         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 146         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 147         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 148         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 149         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 150         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 151         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 152         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 153         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 154         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 155         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 156         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 157         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 158         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 159         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 160         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 161         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 162 };
 163
 164 static const struct pad_config romstage_gpio_table[] = {
 165         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 166         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 167 };
 168
 169 const struct pad_config *variant_gpio_override_table(size_t *num)
 170 {
 171         *num = ARRAY_SIZE(override_gpio_table);
 172         return override_gpio_table;
 173 }
 174
 175 const struct pad_config *variant_early_gpio_table(size_t *num)
 176 {
 177         *num = ARRAY_SIZE(early_gpio_table);
 178         return early_gpio_table;
 179 }
 180
 181 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 182 {
 183         *num = ARRAY_SIZE(romstage_gpio_table);
 184         return romstage_gpio_table;
 185 }