util/crossgcc/buildgcc: Add riscv64-elf to targets
[coreboot.git] / src / mainboard / google / brya / variants / glassway / variant.c
blob5058516d364119b9d293e678746ac903a97d70ad
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <baseboard/variants.h>
4 #include <chip.h>
5 #include <fw_config.h>
6 #include <sar.h>
8 const char *get_wifi_sar_cbfs_filename(void)
10 return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID));
13 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
15 if (fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) {
16 printk(BIOS_INFO, "Enable DDI PORT 2 for HPD and DDC.\n");
17 config->ddi_ports_config[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC;
20 if (!fw_config_probe(FW_CONFIG(WFC, WFC_PRESENT))) {
21 printk(BIOS_INFO, "Disable usb2_port7 of WFC.\n");
22 config->usb2_ports[6].enable = 0;
23 config->usb2_ports[6].ocpin = OC_SKIP;
24 config->usb2_ports[6].tx_bias = USB2_BIAS_0MV;
25 config->usb2_ports[6].tx_emp_enable = USB2_EMP_OFF;
26 config->usb2_ports[6].pre_emp_bias = USB2_BIAS_0MV;
27 config->usb2_ports[6].pre_emp_bit = USB2_HALF_BIT_PRE_EMP;