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mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support
[coreboot.git] / src / mainboard / google / brya / variants / gothrax / overridetree.cb
blob32b5d348f919672139a620d1873c916b21f82cba
1 fw_config
2 field DB_USB 0 1
3 option DB_NONE 0
4 option DB_C_A 1
5 option DB_C_A_LTE 2
6 option DB_A_HDMI_LTE 3
7 end
8 field THERMAL_SOLUTION 2
9 option THERMAL_SOLUTION_PASSIVE 0
10 option THERMAL_SOLUTION_ACTIVE 1
11 end
12 field WLAN 3 4
13 option WLAN_MT7921_AZUREWAVE 0
14 option WLAN_AX211_Intel 1
15 end
16 field AUDIO 5 6
17 option AUDIO_ALC1019_ALC5682IVS 0
18 end
19 field STYLUS 7
20 option STYLUS_ABSENT 0
21 option STYLUS_PRESENT 1
22 end
23 field WFC 8
24 option WFC_PRESENT 0
25 option WFC_ABSENT 1
26 end
27 field TOUCH_PANEL 9
28 option TOUCH_PANEL_I2C_HID 0
29 option TOUCH_PANEL_I2C_GENERIC 1
30 end
31 end
32
33 chip soc/intel/alderlake
34 register "sagv" = "SaGv_Enabled"
35
36 # EMMC Tx CMD Delay
37 # Refer to EDS-Vol2-42.3.7.
38 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
39 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
40 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
41
42 # EMMC TX DATA Delay 1
43 # Refer to EDS-Vol2-42.3.8.
44 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
45 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
46 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
47
48 # EMMC TX DATA Delay 2
49 # Refer to EDS-Vol2-42.3.9.
50 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
51 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
52 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
53 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
54 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
55
56 # EMMC RX CMD/DATA Delay 1
57 # Refer to EDS-Vol2-42.3.10.
58 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
59 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
60 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
61 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
62 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
63
64 # EMMC RX CMD/DATA Delay 2
65 # Refer to EDS-Vol2-42.3.12.
66 # [17:16] stands for Rx Clock before Output Buffer,
67 # 00: Rx clock after output buffer,
68 # 01: Rx clock before output buffer,
69 # 10: Automatic selection based on working mode.
70 # 11: Reserved
71 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
72 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
73 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10005"
74
75 # EMMC Rx Strobe Delay
76 # Refer to EDS-Vol2-42.3.11.
77 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
78 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
79 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"
80
81 # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
82 # Bit 2 - C1 has a redriver which does SBU muxing.
83 # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
84 register "tcss_aux_ori" = "5"
85
86 register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
87 register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
88
89 # Configure external V1P05/Vnn/VnnSx Rails
90 register "ext_fivr_settings" = "{
91 .configure_ext_fivr = 1,
92 .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
93 .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
94 .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
95 .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
96 .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
97 .v1p05_voltage_mv = 1050,
98 .vnn_voltage_mv = 780,
99 .vnn_sx_voltage_mv = 1050,
100 .v1p05_icc_max_ma = 500,
101 .vnn_icc_max_ma = 500,
102 }"
103
104 # Intel Common SoC Config
105 #+-------------------+---------------------------+
106 #| Field | Value |
107 #+-------------------+---------------------------+
108 #| I2C0 | TPM. Early init is |
109 #| | required to set up a BAR |
110 #| | for TPM communication |
111 #| I2C1 | Touchscreen |
112 #| I2C2 | Sub-board(PSensor)/WCAM |
113 #| I2C3 | Audio |
114 #| I2C5 | Trackpad |
115 #+-------------------+---------------------------+
116 register "common_soc_config" = "{
117 .i2c[0] = {
118 .early_init = 1,
119 .speed = I2C_SPEED_FAST_PLUS,
120 .speed_config[0] = {
121 .speed = I2C_SPEED_FAST_PLUS,
122 .scl_lcnt = 55,
123 .scl_hcnt = 30,
124 .sda_hold = 7,
125 }
126 },
127 .i2c[1] = {
128 .speed = I2C_SPEED_FAST,
129 .speed_config[0] = {
130 .speed = I2C_SPEED_FAST,
131 .scl_lcnt = 160,
132 .scl_hcnt = 79,
133 .sda_hold = 7,
134 }
135 },
136 .i2c[2] = {
137 .speed = I2C_SPEED_FAST,
138 .speed_config[0] = {
139 .speed = I2C_SPEED_FAST,
140 .scl_lcnt = 157,
141 .scl_hcnt = 79,
142 .sda_hold = 7,
143 }
144 },
145 .i2c[3] = {
146 .speed = I2C_SPEED_FAST,
147 .speed_config[0] = {
148 .speed = I2C_SPEED_FAST,
149 .scl_lcnt = 157,
150 .scl_hcnt = 79,
151 .sda_hold = 7,
152 }
153 },
154 .i2c[5] = {
155 .speed = I2C_SPEED_FAST,
156 .speed_config[0] = {
157 .speed = I2C_SPEED_FAST,
158 .scl_lcnt = 152,
159 .scl_hcnt = 79,
160 .sda_hold = 7,
161 }
162 },
163 }"
164
165 device domain 0 on
166 device ref dtt on
167 chip drivers/intel/dptf
168 ## sensor information
169 register "options.tsr[0].desc" = ""Memory""
170 register "options.tsr[1].desc" = ""Charger""
171 register "options.tsr[2].desc" = ""Ambient""
172
173 # TODO: below values are initial reference values only
174 ## Passive Policy
175 register "policies.passive" = "{
176 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
177 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
178 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
179 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
180 }"
181
182 ## Critical Policy
183 register "policies.critical" = "{
184 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
185 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
186 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
187 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
188 }"
189
190 register "controls.power_limits" = "{
191 .pl1 = {
192 .min_power = 3000,
193 .max_power = 6000,
194 .time_window_min = 28 * MSECS_PER_SEC,
195 .time_window_max = 32 * MSECS_PER_SEC,
196 .granularity = 200
197 },
198 .pl2 = {
199 .min_power = 25000,
200 .max_power = 25000,
201 .time_window_min = 28 * MSECS_PER_SEC,
202 .time_window_max = 32 * MSECS_PER_SEC,
203 .granularity = 1000
204 }
205 }"
206
207 ## Charger Performance Control (Control, mA)
208 register "controls.charger_perf" = "{
209 [0] = { 255, 1700 },
210 [1] = { 24, 1500 },
211 [2] = { 16, 1000 },
212 [3] = { 8, 500 }
213 }"
214
215 device generic 0 on end
216 end
217 end
218 device ref i2c1 on
219 chip drivers/i2c/hid
220 register "generic.hid" = ""ELAN7B13""
221 register "generic.desc" = ""ELAN Touchscreen""
222 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
223 register "generic.detect" = "1"
224 register "generic.reset_gpio" =
225 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
226 register "generic.reset_delay_ms" = "300"
227 register "generic.reset_off_delay_ms" = "2"
228 register "generic.enable_gpio" =
229 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
230 register "generic.enable_delay_ms" = "6"
231 register "generic.has_power_resource" = "1"
232 register "hid_desc_reg_offset" = "0x01"
233 device i2c 0x10 on
234 probe TOUCH_PANEL TOUCH_PANEL_I2C_HID
235 end
236 end
237 chip drivers/i2c/hid
238 register "generic.hid" = ""ILI2901""
239 register "generic.desc" = ""ILI Touchscreen""
240 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
241 register "generic.detect" = "1"
242 register "generic.reset_gpio" =
243 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
244 register "generic.reset_delay_ms" = "200"
245 register "generic.reset_off_delay_ms" = "2"
246 register "generic.enable_gpio" =
247 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
248 register "generic.enable_delay_ms" = "6"
249 register "generic.has_power_resource" = "1"
250 register "hid_desc_reg_offset" = "0x01"
251 device i2c 0x41 on
252 probe TOUCH_PANEL TOUCH_PANEL_I2C_HID
253 end
254 end
255 chip drivers/i2c/generic
256 register "hid" = ""ELAN0001""
257 register "desc" = ""ELAN Touchscreen""
258 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
259 register "detect" = "1"
260 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
261 register "reset_delay_ms" = "150"
262 register "reset_off_delay_ms" = "1"
263 register "enable_gpio" =
264 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
265 register "enable_delay_ms" = "6"
266 register "has_power_resource" = "true"
267 device i2c 10 on
268 probe TOUCH_PANEL TOUCH_PANEL_I2C_GENERIC
269 end
270 end
271 end
272 device ref i2c2 on
273 chip drivers/i2c/sx9324
274 register "desc" = ""SAR2 Proximity Sensor""
275 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
276 register "speed" = "I2C_SPEED_FAST"
277 register "uid" = "1"
278 register "reg_gnrl_ctrl0" = "0x16"
279 register "reg_gnrl_ctrl1" = "0x21"
280 register "reg_afe_ctrl0" = "0x20"
281 register "reg_afe_ctrl1" = "0x10"
282 register "reg_afe_ctrl2" = "0x00"
283 register "reg_afe_ctrl3" = "0x01"
284 register "reg_afe_ctrl4" = "0x46"
285 register "reg_afe_ctrl5" = "0x00"
286 register "reg_afe_ctrl6" = "0x00"
287 register "reg_afe_ctrl7" = "0x07"
288 register "reg_afe_ctrl8" = "0x12"
289 register "reg_afe_ctrl9" = "0x0f"
290 register "reg_prox_ctrl0" = "0x12"
291 register "reg_prox_ctrl1" = "0x12"
292 register "reg_prox_ctrl2" = "0x90"
293 register "reg_prox_ctrl3" = "0x60"
294 register "reg_prox_ctrl4" = "0x0c"
295 register "reg_prox_ctrl5" = "0x12"
296 register "reg_prox_ctrl6" = "0x3c"
297 register "reg_prox_ctrl7" = "0x58"
298 register "reg_adv_ctrl0" = "0x00"
299 register "reg_adv_ctrl1" = "0x00"
300 register "reg_adv_ctrl2" = "0x00"
301 register "reg_adv_ctrl3" = "0x00"
302 register "reg_adv_ctrl4" = "0x00"
303 register "reg_adv_ctrl5" = "0x05"
304 register "reg_adv_ctrl6" = "0x00"
305 register "reg_adv_ctrl7" = "0x00"
306 register "reg_adv_ctrl8" = "0x00"
307 register "reg_adv_ctrl9" = "0x00"
308 register "reg_adv_ctrl10" = "0x5c"
309 register "reg_adv_ctrl11" = "0x52"
310 register "reg_adv_ctrl12" = "0xb5"
311 register "reg_adv_ctrl13" = "0x00"
312 register "reg_adv_ctrl14" = "0x80"
313 register "reg_adv_ctrl15" = "0x0c"
314 register "reg_adv_ctrl16" = "0x38"
315 register "reg_adv_ctrl17" = "0x56"
316 register "reg_adv_ctrl18" = "0x33"
317 register "reg_adv_ctrl19" = "0xf0"
318 register "reg_adv_ctrl20" = "0xf0"
319
320 register "ph0_pin" = "{1, 3, 3}"
321 register "ph1_pin" = "{3, 2, 1}"
322 register "ph2_pin" = "{3, 3, 1}"
323 register "ph3_pin" = "{1, 3, 3}"
324 register "ph01_resolution" = "512"
325 register "ph23_resolution" = "1024"
326 register "startup_sensor" = "1"
327 register "ph01_proxraw_strength" = "2"
328 register "ph23_proxraw_strength" = "2"
329 register "avg_pos_strength" = "256"
330 register "cs_idle_sleep" = ""gnd""
331 register "int_comp_resistor" = ""lowest""
332 register "input_precharge_resistor_ohms" = "4000"
333 register "input_analog_gain" = "3"
334 device i2c 28 on
335 probe DB_USB DB_C_A_LTE
336 probe DB_USB DB_A_HDMI_LTE
337 end
338 end
339 end
340 device ref i2c3 on
341 chip drivers/i2c/generic
342 register "hid" = ""RTL5682""
343 register "name" = ""RT58""
344 register "desc" = ""Headset Codec""
345 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
346 # Set the jd_src to RT5668_JD1 for jack detection
347 register "property_count" = "1"
348 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
349 register "property_list[0].name" = ""realtek,jd-src""
350 register "property_list[0].integer" = "1"
351 device i2c 1a on end
352 end
353 chip drivers/generic/alc1015
354 register "hid" = ""RTL1019""
355 register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
356 device generic 0 on end
357 end
358 end
359
360 device ref i2c5 on
361 chip drivers/i2c/hid
362 register "generic.hid" = ""PNP0C50""
363 register "generic.desc" = ""PIXART Touchpad""
364 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
365 register "generic.wake" = "GPE0_DW2_14"
366 register "generic.detect" = "1"
367 register "hid_desc_reg_offset" = "0x01"
368 device i2c 15 on end
369 end
370 end
371 device ref pcie_rp4 on
372 # PCIe 4 WLAN
373 register "pch_pcie_rp[PCH_RP(4)]" = "{
374 .clk_src = 2,
375 .clk_req = 2,
376 .flags = PCIE_RP_LTR | PCIE_RP_AER,
377 }"
378 chip drivers/wifi/generic
379 register "wake" = "GPE0_DW1_03"
380 register "add_acpi_dma_property" = "true"
381 device pci 00.0 on end
382 end
383 end
384 device ref pcie_rp7 on
385 # Enable SD Card PCIe 7 using clk 3
386 register "pch_pcie_rp[PCH_RP(7)]" = "{
387 .clk_src = 3,
388 .clk_req = 3,
389 .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
390 }"
391 chip soc/intel/common/block/pcie/rtd3
392 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
393 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
394 register "srcclk_pin" = "3"
395 device generic 0 on end
396 end
397 end
398 device ref pch_espi on
399 chip ec/google/chromeec
400 use conn0 as mux_conn[0]
401 use conn1 as mux_conn[1]
402 device pnp 0c09.0 on end
403 end
404 end
405 device ref pmc hidden
406 chip drivers/intel/pmc_mux
407 device generic 0 on
408 chip drivers/intel/pmc_mux/conn
409 use usb2_port1 as usb2_port
410 use tcss_usb3_port1 as usb3_port
411 device generic 0 alias conn0 on end
412 end
413 chip drivers/intel/pmc_mux/conn
414 use usb2_port2 as usb2_port
415 use tcss_usb3_port2 as usb3_port
416 device generic 1 alias conn1 on
417 probe DB_USB DB_C_A
418 probe DB_USB DB_C_A_LTE
419 end
420 end
421 end
422 end
423 end
424 device ref tcss_xhci on
425 chip drivers/usb/acpi
426 device ref tcss_root_hub on
427 chip drivers/usb/acpi
428 register "desc" = ""USB3 Type-C Port C0 (MLB)""
429 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
430 register "use_custom_pld" = "true"
431 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
432 device ref tcss_usb3_port1 on end
433 end
434 chip drivers/usb/acpi
435 register "desc" = ""USB3 Type-C Port C1 (DB)""
436 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
437 register "use_custom_pld" = "true"
438 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
439 device ref tcss_usb3_port2 on
440 probe DB_USB DB_C_A
441 probe DB_USB DB_C_A_LTE
442 end
443 end
444 end
445 end
446 end
447 device ref xhci on
448 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
449 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC
450 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
451 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
452 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1
453
454 chip drivers/usb/acpi
455 device ref xhci_root_hub on
456 chip drivers/usb/acpi
457 register "desc" = ""USB2 Type-C Port C0 (MLB)""
458 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
459 register "use_custom_pld" = "true"
460 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
461 device ref usb2_port1 on end
462 end
463 chip drivers/usb/acpi
464 register "desc" = ""USB2 Type-C Port C1 (DB)""
465 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
466 register "use_custom_pld" = "true"
467 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
468 device ref usb2_port2 on
469 probe DB_USB DB_C_A
470 probe DB_USB DB_C_A_LTE
471 end
472 end
473 chip drivers/usb/acpi
474 register "desc" = ""USB2 Type-A Port A0 (MLB)""
475 register "type" = "UPC_TYPE_A"
476 register "use_custom_pld" = "true"
477 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
478 device ref usb2_port3 on end
479 end
480 chip drivers/usb/acpi
481 register "desc" = ""USB2 Type-A Port A1 (DB)""
482 register "type" = "UPC_TYPE_A"
483 register "use_custom_pld" = "true"
484 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
485 device ref usb2_port4 on end
486 end
487 chip drivers/usb/acpi
488 register "desc" = ""USB2 WWAN""
489 register "type" = "UPC_TYPE_INTERNAL"
490 device ref usb2_port5 on
491 probe DB_USB DB_C_A_LTE
492 probe DB_USB DB_A_HDMI_LTE
493 end
494 end
495 chip drivers/usb/acpi
496 register "desc" = ""USB2 UFC""
497 register "type" = "UPC_TYPE_INTERNAL"
498 device ref usb2_port6 on end
499 end
500 chip drivers/usb/acpi
501 register "desc" = ""USB2 WFC""
502 register "type" = "UPC_TYPE_INTERNAL"
503 device ref usb2_port7 on
504 probe WFC WFC_PRESENT
505 end
506 end
507 chip drivers/usb/acpi
508 register "desc" = ""USB2 Bluetooth""
509 register "type" = "UPC_TYPE_INTERNAL"
510 register "reset_gpio" =
511 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
512 device ref usb2_port8 on end
513 end
514 chip drivers/usb/acpi
515 register "desc" = ""CNVi Bluetooth""
516 register "type" = "UPC_TYPE_INTERNAL"
517 register "reset_gpio" =
518 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
519 device ref usb2_port10 on end
520 end
521 chip drivers/usb/acpi
522 register "desc" = ""USB3 Type-A Port A0 (MLB)""
523 register "type" = "UPC_TYPE_USB3_A"
524 register "use_custom_pld" = "true"
525 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
526 device ref usb3_port1 on end
527 end
528 chip drivers/usb/acpi
529 register "desc" = ""USB3 Type-A Port A1 (DB)""
530 register "type" = "UPC_TYPE_USB3_A"
531 register "use_custom_pld" = "true"
532 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
533 device ref usb3_port2 on end
534 end
535 chip drivers/usb/acpi
536 register "desc" = ""USB3 WWAN""
537 register "type" = "UPC_TYPE_INTERNAL"
538 device ref usb3_port3 on
539 probe DB_USB DB_C_A_LTE
540 probe DB_USB DB_A_HDMI_LTE
541 end
542 end
543 end
544 end
545 end
546 device ref hda on
547 chip drivers/sof
548 register "spkr_tplg" = "rt1019"
549 register "jack_tplg" = "rt5682"
550 register "mic_tplg" = "_2ch_pdm0"
551 device generic 0 on end
552 end
553 end
554 end
555 end
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