mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support

[coreboot.git] / src / mainboard / google / brya / variants / lisbon / overridetree.cb

fw_config
        field STORAGE 1 1
                option STORAGE_EMMC     0
                option STORAGE_NVME     1
        end
end

chip soc/intel/alderlake
        register "sagv" = "SaGv_Enabled"

        # Intel Common SoC Config
        #+-------------------+---------------------------+
        #| Field             |  Value                    |
        #+-------------------+---------------------------+
        #| GSPI1             | NC                        |
        #| I2C0              | Audio                     |
        #| I2C1              | cr50 TPM. Early init is   |
        #|                   | required to set up a BAR  |
        #|                   | for TPM communication     |
        #| I2C3              | NC                        |
        #| I2C5              | NC                        |
        #+-------------------+---------------------------+
        register "common_soc_config" = "{
                .i2c[0] = {
                        .speed = I2C_SPEED_FAST,
                        .rise_time_ns = 600,
                        .fall_time_ns = 400,
                        .data_hold_time_ns = 50,
                },
                .i2c[1] = {
                        .early_init = 1,
                        .speed = I2C_SPEED_FAST,
                        .rise_time_ns = 600,
                        .fall_time_ns = 400,
                        .data_hold_time_ns = 50,
                },
        }"

        register "usb2_ports[0]" = "USB2_PORT_MAX_TYPE_C(OC2)"  # set to Max for USB2_C0
        register "usb2_ports[1]" = "USB2_PORT_EMPTY"            # Disable Port 1
        register "usb2_ports[2]" = "USB2_PORT_EMPTY"            # Disable Port 2
        register "usb2_ports[3]" = "USB2_PORT_EMPTY"            # Disable Port 3
        register "usb2_ports[4]" = "USB2_PORT_EMPTY"            # Disable Port 4

        register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A0
        register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A1(DCI)
        register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A2
        register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A3

        register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"     # USB TYPE C
        register "tcss_ports[2]" = "TCSS_PORT_EMPTY"            # Disable Port2

        register "serial_io_gspi_mode" = "{
                [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
                [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
        }"

        register "ddi_ports_config" = "{
                [DDI_PORT_A] = DDI_ENABLE_HPD,
                [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
                [DDI_PORT_1] = DDI_ENABLE_HPD,
                [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
        }"

        device domain 0 on
                device ref dtt on
                        chip drivers/intel/dptf
                                ## sensor information
                                register "options.tsr[0].desc" = ""DRAM""
                                register "options.tsr[1].desc" = ""Charger""

                                # TODO: below values are initial reference values only
                                ## Active Policy
                                register "policies.active" = "{
                                        [0] = {
                                                .target = DPTF_CPU,
                                                .thresholds = {
                                                                TEMP_PCT(85, 90),
                                                                TEMP_PCT(80, 80),
                                                                TEMP_PCT(75, 70),
                                                }
                                        }
                                }"

                                ## Passive Policy
                                register "policies.passive" = "{
                                        [0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
                                        [1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
                                        [2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
                                }"

                                ## Critical Policy
                                register "policies.critical" = "{
                                        [0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
                                        [1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
                                        [2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
                                }"

                                register "controls.power_limits" = "{
                                        .pl1 = {
                                                        .min_power = 3000,
                                                        .max_power = 15000,
                                                        .time_window_min = 28 * MSECS_PER_SEC,
                                                        .time_window_max = 32 * MSECS_PER_SEC,
                                                        .granularity = 200,
                                                },
                                        .pl2 = {
                                                        .min_power = 55000,
                                                        .max_power = 55000,
                                                        .time_window_min = 28 * MSECS_PER_SEC,
                                                        .time_window_max = 32 * MSECS_PER_SEC,
                                                        .granularity = 1000,
                                                }
                                }"

                                ## Charger Performance Control (Control, mA)
                                register "controls.charger_perf" = "{
                                        [0] = { 255, 1700 },
                                        [1] = {  24, 1500 },
                                        [2] = {  16, 1000 },
                                        [3] = {   8,  500 }
                                }"

                                ## Fan Performance Control (Percent, Speed, Noise, Power)
                                register "controls.fan_perf" = "{
                                        [0] = {  90, 6700, 220, 2200, },
                                        [1] = {  80, 5800, 180, 1800, },
                                        [2] = {  70, 5000, 145, 1450, },
                                        [3] = {  60, 4900, 115, 1150, },
                                        [4] = {  50, 3838,  90,  900, },
                                        [5] = {  40, 2904,  55,  550, },
                                        [6] = {  30, 2337,  30,  300, },
                                        [7] = {  20, 1608,  15,  150, },
                                        [8] = {  10,  800,  10,  100, },
                                        [9] = {   0,    0,   0,   50, }
                                }"

                                ## Fan options
                                register "options.fan.fine_grained_control" = "true"
                                register "options.fan.step_size" = "2"

                                device generic 0 alias dptf_policy on end
                        end
                end
                device ref pcie4_0 on
                        # Enable CPU PCIE RP 1 using CLK 0
                        register "cpu_pcie_rp[CPU_RP(1)]" = "{
                                .clk_req = 0,
                                .clk_src = 0,
                                .flags = PCIE_RP_LTR | PCIE_RP_AER,
                        }"
                        probe STORAGE STORAGE_NVME
                end #NVMe
                device ref tbt_pcie_rp0 off end
                device ref tbt_pcie_rp1 off end
                device ref tbt_pcie_rp2 off end

                device ref tcss_dma0 off end
                device ref tcss_dma1 off end
                device ref cnvi_wifi on
                        chip drivers/wifi/generic
                                register "wake" = "GPE0_PME_B0"
                                device generic 0 on end
                        end
                end
                device ref i2c0 on
                        chip drivers/i2c/generic
                                register "hid" = ""RTL5682""
                                register "name" = ""RT58""
                                register "desc" = ""Headset Codec""
                                register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
                                # Set the jd_src to RT5668_JD1 for jack detection
                                register "property_count" = "1"
                                register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
                                register "property_list[0].name" = ""realtek,jd-src""
                                register "property_list[0].integer" = "1"
                                device i2c 1a on end
                        end
                end #I2C0
                device ref i2c1 on
                        chip drivers/i2c/tpm
                                register "hid" = ""GOOG0005""
                                register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
                                device i2c 50 on end
                        end
                end
                device ref pcie_rp7 on
                        chip drivers/net
                                register "wake" = "GPE0_DW0_07"
                                register "customized_leds" = "0x060f"
                                register "enable_aspm_l1_2" = "1"
                                register "add_acpi_dma_property" = "true"
                                device pci 00.0 on end
                        end
                end # RTL8111 Ethernet NIC
                device ref pcie_rp8 on
                        chip soc/intel/common/block/pcie/rtd3
                                register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
                                register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
                                register "srcclk_pin" = "3"
                                device generic 0 on end
                        end
                end     #PCIE8 SD card
                device ref pcie_rp12 on
                        # Enable PCIE eMMC bridge 12 using clk 4
                        register "pch_pcie_rp[PCH_RP(12)]" = "{
                                .clk_src = 4,
                                .clk_req = 4,
                                .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
                        }"
                        probe STORAGE STORAGE_EMMC
                end     #PCIE12 EMMC
                device ref gspi1 off end
                device ref pch_espi on
                        chip ec/google/chromeec
                                use conn0 as mux_conn[0]
                                device pnp 0c09.0 on end
                        end
                end
                device ref pmc hidden
                        chip drivers/intel/pmc_mux
                                device generic 0 on
                                        chip drivers/intel/pmc_mux/conn
                                                use usb2_port1 as usb2_port
                                                use tcss_usb3_port1 as usb3_port
                                                device generic 0 alias conn0 on end
                                        end
                                end
                        end
                end
                device ref tcss_xhci on
                        chip drivers/usb/acpi
                                device ref tcss_root_hub on
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-C Port C0 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
                                                device ref tcss_usb3_port1 on end
                                        end
                                end
                        end
                end
                device ref xhci on
                        chip drivers/usb/acpi
                                device ref xhci_root_hub on
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-C Port C0 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
                                                device ref usb2_port1 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-A Port A3 (MLB)""
                                                register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
                                                device ref usb2_port6 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-A Port A2 (MLB)""
                                                register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
                                                device ref usb2_port7 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-A Port A1 (MLB)""
                                                register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
                                                device ref usb2_port8 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-A Port A0 (MLB)""
                                                register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
                                                device ref usb2_port9 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Bluetooth""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                register "reset_gpio" =
                                                        "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
                                                device ref usb2_port10 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-A Port A0 (MLB)""
                                                register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
                                                device ref usb3_port1 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-A Port A1 (MLB)""
                                                register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
                                                device ref usb3_port2 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-A Port A2 (MLB)""
                                                register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
                                                device ref usb3_port3 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-A Port A3 (MLB)""
                                                register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
                                                device ref usb3_port4 on end
                                        end
                                end
                        end
                end
        end
end