src/mainboard/google/brya/variants/marasov/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/variants.h>
   4 #include <boardid.h>
   5 #include <intelblocks/early_graphics.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A5  : ESPI_ALERT0# ==> NC */
  11         PAD_NC(GPP_A5, NONE),
  12         /* A6  : ESPI_ALERT1# ==> NC */
  13         PAD_NC(GPP_A6, NONE),
  14         /* A7  : SRCCLK_OE7# ==> NC */
  15         PAD_NC(GPP_A7, NONE),
  16         /* A8  : WWAN_RF_DISABLE_ODL ==> NC */
  17         PAD_NC(GPP_A8, NONE),
  18         /* A9  : ESPI_CLK ==> ESPI_CLK */
  19         PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
  20         /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */
  21         PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
  22         /* A12 : EN_PP3300_WWAN ==> NC */
  23         PAD_NC(GPP_A12, NONE),
  24         /* A19 : USB_C2_AUX_DC_P ==> NC */
  25         PAD_NC(GPP_A19, NONE),
  26         /* A20 : USB_C2_AUX_DC_N ==> NC */
  27         PAD_NC(GPP_A20, NONE),
  28         /* A21 : USB_C1_AUX_DC_P ==> NC */
  29         PAD_NC(GPP_A21, NONE),
  30         /* A22 : USB_C1_AUX_DC_N ==> NC */
  31         PAD_NC(GPP_A22, NONE),
  32         /* B2  : GPP_B2(TP97) ==> GPP_B2(TP1712) */
  33         PAD_NC(GPP_B2, NONE),
  34         /* B3  : PROC_GP2 ==> NC */
  35         PAD_NC(GPP_B3, NONE),
  36         /* B5  : PCH_I2C_MISC_SDA ==> NC */
  37         PAD_NC(GPP_B5, NONE),
  38         /* B6  : PCH_I2C_MISC_SCL ==> NC */
  39         PAD_NC(GPP_B6, NONE),
  40         /* B7  : PCH_I2C_TCHSCR_SDA ==> PCH_I2C_TCHSCR_SDA */
  41         PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
  42         /* B8  : PCH_I2C_TCHSCR_SCL ==> PCH_I2C_TCHSCR_SCL */
  43         PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
  44         /* B15 : FP_USER_PRES_FP_L ==> NC */
  45         PAD_NC(GPP_B15, NONE),
  46         /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
  47         PAD_CFG_NF_LOCK(GPP_B23, DN_20K, NF2, LOCK_CONFIG),
  48         /* C3  : EN_UCAM_PWR ==> EN_UCAM_PWR(TP1103) */
  49         PAD_NC(GPP_C3, NONE),
  50         /* C4  : EN_UCAM_SENR_PWR ==> EN_UCAM_SENR_PWR(TP1104) */
  51         PAD_NC(GPP_C4, NONE),
  52         /* D0  : ISH_GP0 ==> NC */
  53         PAD_NC(GPP_D0, NONE),
  54         /* D3  : ISH_GP3 ==> NC */
  55         PAD_NC(GPP_D3, NONE),
  56         /* D5  : WWAN_DPR_SAR_ODL ==> NC */
  57         PAD_NC(GPP_D5, NONE),
  58         /* D8  : SD_CLKREQ_ODL ==> NC */
  59         PAD_NC(GPP_D8, NONE),
  60         /* D9  : USB_C2_LSX_TX ==> NC */
  61         PAD_NC(GPP_D9, NONE),
  62         /* D10 : ISH_SPI_CLK ==> NC */
  63         PAD_NC(GPP_D10, NONE),
  64         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
  65         PAD_CFG_GPO(GPP_D11, 1, DEEP),
  66         /* D13 : ISH_UART0_RXD ==> NC */
  67         PAD_NC(GPP_D13, NONE),
  68         /* D14 : ISH_UART0_TXD ==> NC */
  69         PAD_NC(GPP_D14, NONE),
  70         /* D15 : ISH_UART0_RTS# ==> NC */
  71         PAD_NC(GPP_D15, NONE),
  72         /* D16 : ISH_UART0_CTS# ==> NC */
  73         PAD_NC(GPP_D16, NONE),
  74         /* D17 : UART1_RXD ==> NC */
  75         PAD_NC(GPP_D17, NONE),
  76         /* D18 : UART1_TXD ==> NC */
  77         PAD_NC(GPP_D18, NONE),
  78         /* E0 : WWAN_PERST_L ==> NC */
  79         PAD_NC(GPP_E0, NONE),
  80         /* E3  : PROC_GP0 ==> NC */
  81         PAD_NC(GPP_E3, NONE),
  82         /* E4  : SATA_DEVSLP0 ==> NC */
  83         PAD_NC(GPP_E4, NONE),
  84         /* E5  : SATA_DEVSLP1 ==> NC */
  85         PAD_NC(GPP_E5, NONE),
  86         /* E7  : PROC_GP1 ==> NC */
  87         PAD_NC(GPP_E7, NONE),
  88         /* E10 : WWAN_CONFIG0 ==> NC */
  89         PAD_NC(GPP_E10, NONE),
  90         /* E16 : WWAN_RST_L ==> NC */
  91         PAD_NC(GPP_E16, NONE),
  92         /* E17 : WWAN_CONFIG2 ==> SSD_STRAP */
  93         PAD_CFG_GPI(GPP_E17, NONE, DEEP),
  94         /* E18 : USB_C0_LSX_TX ==> NC */
  95         PAD_NC(GPP_E18, NONE),
  96         /* E19 : DDP1_CTRLDATA ==> NC */
  97         PAD_NC(GPP_E19, NONE),
  98         /* E20 : USB_C1_LSX_TX ==> NC */
  99         PAD_NC(GPP_E20, NONE),
 100         /* E21 : DDP2_CTRLDATA ==> NC */
 101         PAD_NC(GPP_E21, NONE),
 102         /* F6  : WWAN_WLAN_COEX3 ==> NC */
 103         PAD_NC(GPP_F6, NONE),
 104         /* F11 : THC1_SPI2_CLK ==> NC */
 105         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
 106         /* F12 : GSXDOUT ==> NC */
 107         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
 108         /* F13 : GSXDOUT ==> NC */
 109         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
 110         /* F15 : GSXSRESET# ==> NC */
 111         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
 112         /* F16 : GSXCLK ==> NC */
 113         PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
 114         /* F19 : GPP_F19(TP93) ==> NC */
 115         PAD_NC(GPP_F19, NONE),
 116         /* F20 : UCAM_RST_L ==> NC */
 117         PAD_NC(GPP_F20, NONE),
 118         /* F21 : WWAN_FCPO_L ==> NC */
 119         PAD_NC(GPP_F21, NONE),
 120         /* F23 : NC */
 121         PAD_CFG_NF_LOCK(GPP_F23, NONE, NF1, LOCK_CONFIG),
 122         /* H8  : WWAN_WLAN_COEX1 ==> PCB_ID0(NC) */
 123         PAD_CFG_GPI_LOCK(GPP_H8, NONE, LOCK_CONFIG),
 124         /* H9  : WWAN_WLAN_COEX2 ==> PCB_ID1(NC) */
 125         PAD_CFG_GPI_LOCK(GPP_H9, NONE, LOCK_CONFIG),
 126         /* H12 : I2C7_SDA ==> NC */
 127         PAD_NC(GPP_H12, NONE),
 128         /* H19 : SRCCLKREQ4# ==> NC */
 129         PAD_NC(GPP_H19, NONE),
 130         /* H21 : UCAM_MCLK ==>  NC */
 131         PAD_NC(GPP_H21, NONE),
 132         /* H22 : WCAM_MCLK ==> NC */
 133         PAD_NC(GPP_H22, NONE),
 134         /* H23 : WWAN_CLKREQ_ODL ==> NC */
 135         PAD_NC(GPP_H23, NONE),
 136         /* R4 : HDA_RST# ==> NC */
 137         PAD_NC(GPP_R4, NONE),
 138         /* R5 : HDA_SDI1 ==> NC */
 139         PAD_NC(GPP_R5, NONE),
 140         /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */
 141         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
 142         /* R7 : I2S2_RXD ==> I2S_PCH_RX_SPKR_TX */
 143         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
 144         /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */
 145         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
 146         /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */
 147         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
 148         /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */
 149         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
 150         /* S3 : SNDW1_DATA ==> NC */
 151         PAD_NC(GPP_S3, NONE),
 152         /* S4 : SDW_SPKR_CLK ==> NC */
 153         PAD_NC(GPP_S4, NONE),
 154         /* S5 : SDW_SPKR_DATA ==> NC */
 155         PAD_NC(GPP_S5, NONE),
 156         /* S6 : DMIC_CLK1_R ==> NC */
 157         PAD_NC(GPP_S6, NONE),
 158         /* S7 : DMIC_DATA1_R ==> NC */
 159         PAD_NC(GPP_S7, NONE),
 160         /* GPD11: LANPHYC ==> NC */
 161         PAD_NC(GPD11, NONE),
 162 };
 163
 164 /* Early pad configuration in bootblock */
 165 static const struct pad_config early_gpio_table[] = {
 166         /* A13 : GSC_PCH_INT_ODL ==> GSC_PCH_INT_ODL */
 167         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 168         /* B4  : SSD_PERST_L ==> SSD_PERST_L */
 169         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 170         /* B7  : PCH_I2C_TCHSCR_SDA ==> PCH_I2C_TCHSCR_SDA */
 171         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
 172         /* B8  : PCH_I2C_TCHSCR_SCL ==> PCH_I2C_TCHSCR_SCL */
 173         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
 174
 175         /*
 176          * D1  : FP_RST_ODL ==> FP_RST_ODL
 177          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 178          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 179          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 180          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 181          * FPMCU not working after a S3 resume. This is a known issue.
 182          */
 183         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 184         /* D2  : EN_FP_PWR ==> EN_FP_PWR */
 185         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 186         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 187         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 188         /* E0  : WWAN_PERST_L ==> NC */
 189         PAD_NC(GPP_E0, NONE),
 190         /* E13 : MEM_CH_SEL ==> MEM_CH_SEL */
 191         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 192         /* E15 : PCH_WP_OD ==> PCH_WP_OD */
 193         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 194         /* E16 : WWAN_RST_L ==> NC */
 195         PAD_NC(GPP_E16, NONE),
 196         /* F18 : EC_IN_RW_OD ==> EC_IN_RW_OD */
 197         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 198         /* H6  : PCH_I2C_TPM_SDA ==> PCH_I2C_TPM_SDA */
 199         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 200         /* H7  : PCH_I2C_TPM_SCL ==> PCH_I2C_TPM_SCL */
 201         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 202         /* H10 : UART_PCH_RX_DBG_TX ==> UART_PCH_RX_DBG_TX */
 203         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 204         /* H11 : UART_PCH_TX_DBG_RX ==> UART_PCH_TX_DBG_RX */
 205         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 206         /* H13 : EN_PP3300_SD ==> EN_PP3300_SD(TP1201) */
 207         PAD_NC(GPP_H13, UP_20K),
 208 };
 209
 210 static const struct pad_config romstage_gpio_table[] = {
 211         /* B4  : SSD_PERST_L ==> SSD_PERST_L */
 212         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 213
 214         /* Enable touchscreen, hold in reset */
 215         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 216         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 217         /* C1  : SMBDATA ==> USI_RST_L */
 218         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 219
 220         /* D1  : FP_RST_ODL ==> FP_RST_ODL */
 221         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 222         /* D2  : EN_FP_PWR ==> EN_FP_PWR */
 223         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 224 };
 225
 226 static const struct pad_config early_graphics_gpio_table[] = {
 227         /* F9  : BOOTMPC ==> SLP_S0_GATE_R */
 228         PAD_CFG_GPO(GPP_F9, 1, PLTRST),
 229 };
 230
 231 const struct pad_config *variant_early_graphics_gpio_table(size_t *num)
 232 {
 233         *num = ARRAY_SIZE(early_graphics_gpio_table);
 234         return early_graphics_gpio_table;
 235 }
 236
 237 const struct pad_config *variant_gpio_override_table(size_t *num)
 238 {
 239         *num = ARRAY_SIZE(override_gpio_table);
 240         return override_gpio_table;
 241 }
 242
 243 const struct pad_config *variant_early_gpio_table(size_t *num)
 244 {
 245         *num = ARRAY_SIZE(early_gpio_table);
 246         return early_gpio_table;
 247 }
 248
 249 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 250 {
 251         *num = ARRAY_SIZE(romstage_gpio_table);
 252         return romstage_gpio_table;
 253 }