src/mainboard/google/brya/variants/nivviks/fw_config.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <boardid.h>
   6 #include <console/console.h>
   7 #include <fw_config.h>
   8
   9 static const struct pad_config lte_disable_pads_nivviks[] = {
  10         /* A8  : WWAN_RF_DISABLE_ODL */
  11         PAD_NC(GPP_A8, NONE),
  12         /* D6  : WWAN_EN */
  13         PAD_NC(GPP_D6, NONE),
  14         /* F12 : WWAN_RST_L */
  15         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
  16         /* H19 : SOC_I2C_SUB_INT_ODL */
  17         PAD_NC(GPP_H19, NONE),
  18         /* H23 : WWAN_SAR_DETECT_ODL */
  19         PAD_NC(GPP_H23, NONE),
  20 };
  21
  22 static const struct pad_config lte_disable_pads_nirwen[] = {
  23         /* A8  : WWAN_RF_DISABLE_ODL */
  24         PAD_NC(GPP_A8, NONE),
  25         /* E13  : WWAN_EN */
  26         PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
  27         /* F12 : WWAN_RST_L */
  28         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
  29         /* H19 : SOC_I2C_SUB_INT_ODL */
  30         PAD_NC(GPP_H19, NONE),
  31         /* H23 : WWAN_SAR_DETECT_ODL */
  32         PAD_NC(GPP_H23, NONE),
  33 };
  34
  35 static const struct pad_config sd_disable_pads[] = {
  36         /* D8  : SD_CLKREQ_ODL */
  37         PAD_NC(GPP_D8, NONE),
  38         /* H12 : SD_PERST_L */
  39         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
  40         /* H13 : EN_PP3300_SD_X */
  41         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
  42 };
  43
  44 static const struct pad_config wfc_disable_pads[] = {
  45         /* D3  : WCAM_RST_L */
  46         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  47         /* D15 : EN_PP2800_WCAM_X */
  48         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  49         /* D16 : EN_PP1800_PP1200_WCAM_X */
  50         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  51         /* H22 : WCAM_MCLK_R */
  52         PAD_NC(GPP_H22, NONE),
  53         /* R6 : DMIC_WCAM_CLK_R */
  54         PAD_NC(GPP_R6, NONE),
  55         /* R7 : DMIC_WCAM_DATA */
  56         PAD_NC(GPP_R7, NONE),
  57 };
  58
  59 static const struct pad_config emmc_disable_pads[] = {
  60         /* I7  : EMMC_CMD */
  61         PAD_NC(GPP_I7, NONE),
  62         /* I8  : EMMC_D0 */
  63         PAD_NC(GPP_I8, NONE),
  64         /* I9  : EMMC_D1 */
  65         PAD_NC(GPP_I9, NONE),
  66         /* I10 : EMMC_D2 */
  67         PAD_NC(GPP_I10, NONE),
  68         /* I11 : EMMC_D3 */
  69         PAD_NC(GPP_I11, NONE),
  70         /* I12 : EMMC_D4 */
  71         PAD_NC(GPP_I12, NONE),
  72         /* I13 : EMMC_D5 */
  73         PAD_NC(GPP_I13, NONE),
  74         /* I14 : EMMC_D6 */
  75         PAD_NC(GPP_I14, NONE),
  76         /* I15 : EMMC_D7 */
  77         PAD_NC(GPP_I15, NONE),
  78         /* I16 : EMMC_RCLK */
  79         PAD_NC(GPP_I16, NONE),
  80         /* I17 : EMMC_CLK */
  81         PAD_NC(GPP_I17, NONE),
  82         /* I18 : EMMC_RST_L */
  83         PAD_NC(GPP_I18, NONE),
  84 };
  85
  86 static const struct pad_config nvme_disable_pads[] = {
  87         /* B4  : SSD_PERST_L */
  88         PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG),
  89         /* D6  : SSD_CLKREQ_ODL */
  90         PAD_NC(GPP_D6, NONE),
  91         /* D11 : EN_PP3300_SSD */
  92         PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
  93         /* E17 : SSD_PLN_L */
  94         PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
  95 };
  96
  97 static const struct pad_config wifi_pcie_enable_pad[] = {
  98         /* H3 : SX_EXIT_HOLDOFF => WLAN_PCIE_WAKE_ODL */
  99         PAD_CFG_GPI_IRQ_WAKE(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
 100         /* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
 101         PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 102         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 103         PAD_CFG_GPO_LOCK(GPP_H20, 1, LOCK_CONFIG),
 104 };
 105
 106 static const struct pad_config stylus_disable_pads[] = {
 107         /* F13 : SOC_PEN_DETECT_R_ODL */
 108         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
 109         /* F15 : SOC_PEN_DETECT_ODL */
 110         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
 111 };
 112
 113 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 114 {
 115         if (!fw_config_probe(FW_CONFIG(WIFI_CATEGORY, WIFI_6))) {
 116                 printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n");
 117                 config->cnvi_bt_core = false;
 118                 printk(BIOS_INFO, "CNVi bluetooth audio offload disabled by fw_config\n");
 119                 config->cnvi_bt_audio_offload = false;
 120         }
 121 }
 122
 123 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 124 {
 125         if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
 126                 if (board_id() >= 2) {
 127                         printk(BIOS_INFO, "Disable LTE-related GPIO pins on nirwen.\n");
 128                         gpio_padbased_override(padbased_table, lte_disable_pads_nirwen,
 129                                                         ARRAY_SIZE(lte_disable_pads_nirwen)
 130                         );
 131                 } else {
 132                         printk(BIOS_INFO, "Disable LTE-related GPIO pins on nivviks.\n");
 133                         gpio_padbased_override(padbased_table, lte_disable_pads_nivviks,
 134                                                         ARRAY_SIZE(lte_disable_pads_nivviks)
 135                         );
 136                 }
 137         }
 138
 139         if (fw_config_probe(FW_CONFIG(WIFI_CATEGORY, WIFI_7))) {
 140                 printk(BIOS_INFO, "Enable PCie based Wifi GPIO pins.\n");
 141                 gpio_padbased_override(padbased_table, wifi_pcie_enable_pad,
 142                                                 ARRAY_SIZE(wifi_pcie_enable_pad));
 143         }
 144
 145         if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) {
 146                 printk(BIOS_INFO, "Disable SD card GPIO pins.\n");
 147                 gpio_padbased_override(padbased_table, sd_disable_pads,
 148                                                 ARRAY_SIZE(sd_disable_pads));
 149         }
 150
 151         if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) {
 152                 printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n");
 153                 gpio_padbased_override(padbased_table, wfc_disable_pads,
 154                                                 ARRAY_SIZE(wfc_disable_pads));
 155         }
 156
 157         if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
 158                 printk(BIOS_INFO, "Disable eMMC SSD GPIO pins.\n");
 159                 gpio_padbased_override(padbased_table, emmc_disable_pads,
 160                                                 ARRAY_SIZE(emmc_disable_pads));
 161         }
 162
 163         if (board_id() >= 2 && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
 164                 printk(BIOS_INFO, "Disable NVMe SSD GPIO pins.\n");
 165                 gpio_padbased_override(padbased_table, nvme_disable_pads,
 166                                                 ARRAY_SIZE(nvme_disable_pads));
 167         }
 168
 169         if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) {
 170                 printk(BIOS_INFO, "Disable Stylus GPIO pins.\n");
 171                 gpio_padbased_override(padbased_table, stylus_disable_pads,
 172                                                 ARRAY_SIZE(stylus_disable_pads));
 173         }
 174 }