src/mainboard/google/brya/variants/nivviks/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <boardid.h>
   6 #include <commonlib/helpers.h>
   7 #include <soc/gpio.h>
   8
   9 /* Pad configuration in ramstage for nivviks board_id = 0 */
  10 static const struct pad_config board_id0_overrides[] = {
  11         /* A8  : WWAN_RF_DISABLE_ODL */
  12         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  13         /* D6  : WWAN_EN */
  14         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  15         /* D7  : WLAN_CLKREQ_ODL */
  16         PAD_NC(GPP_D7, NONE),
  17         /* F12 : WWAN_RST_L */
  18         PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
  19         /* H3  : WLAN_PCIE_WAKE_ODL */
  20         PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
  21         /* H19 : SOC_I2C_SUB_INT_ODL */
  22         PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
  23         /* H23 : WWAN_SAR_DETECT_ODL */
  24         PAD_CFG_GPO(GPP_H23, 1, DEEP),
  25         /* R4 : I2S2_SCLK ==> I2S_SPK_BCLK_R */
  26         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),
  27         /* R5 : I2S2_SFRM ==> I2S_SPK_LRCK_R */
  28         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
  29         /* R6 : I2S2_TXD ==> I2S_SPK_AUDIO_R */
  30         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
  31         /* R7 : I2S2_RXD ==> NC */
  32         PAD_NC(GPP_R7, NONE),
  33         /* S0  : NC */
  34         PAD_NC(GPP_S0, NONE),
  35         /* S1  : NC */
  36         PAD_NC(GPP_S1, NONE),
  37         /* S2 : DMIC_CKL_A_0 ==> DMIC_UCAM_CLK_R */
  38         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
  39         /* S3 : DMIC_DATA_0 ==> DMIC_UCAM_DATA */
  40         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
  41         /* S6  : DMIC_CLK_A_1 ==> DMIC_WCAM_CLK_R */
  42         PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
  43         /* S7  : DMIC_DATA_1 ==> DMIC_WCAM_DATA */
  44         PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
  45 };
  46
  47 /* Pad configuration in ramstage for nivviks board_id >= 1 */
  48 static const struct pad_config override_gpio_table[] = {
  49         /* A8  : WWAN_RF_DISABLE_ODL */
  50         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  51         /* D6  : WWAN_EN */
  52         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  53         /* D7  : WLAN_CLKREQ_ODL */
  54         PAD_NC(GPP_D7, NONE),
  55         /* F12 : WWAN_RST_L */
  56         PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
  57         /* H3  : WLAN_PCIE_WAKE_ODL */
  58         PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
  59         /* H19 : SOC_I2C_SUB_INT_ODL */
  60         PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
  61         /* H23 : WWAN_SAR_DETECT_ODL */
  62         PAD_CFG_GPO(GPP_H23, 1, DEEP),
  63
  64         /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
  65         /* BT_I2S_BCLK */
  66         PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
  67         /* BT_I2S_SYNC */
  68         PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
  69         /* BT_I2S_SDO */
  70         PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
  71         /* BT_I2S_SDI */
  72         PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
  73         /* SSP2_SCLK */
  74         PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
  75         /* SSP2_SFRM */
  76         PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
  77         /* SSP_TXD */
  78         PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
  79         /* SSP_RXD */
  80         PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
  81 };
  82
  83 /* Pad configuration in ramstage for nirwen */
  84 static const struct pad_config override_gpio_table_nirwen[] = {
  85         /* A8  : WWAN_RF_DISABLE_ODL */
  86         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  87         /* B4  : SSD_PERST_L */
  88         PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
  89         /* D6  : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
  90         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
  91         /* D7  : WLAN_CLKREQ_ODL */
  92         PAD_NC(GPP_D7, NONE),
  93         /* D11 : EN_PP3300_SSD */
  94         PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG),
  95         /* E13  : SRCCLKREQ1# ==> WWAN_EN */
  96         PAD_CFG_GPO_LOCK(GPP_E13, 1, LOCK_CONFIG),
  97         /* E17 : SSD_PLN_L */
  98         PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
  99         /* F12 : WWAN_RST_L */
 100         PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
 101         /* H3  : WLAN_PCIE_WAKE_ODL */
 102         PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
 103         /* H19 : SOC_I2C_SUB_INT_ODL */
 104         PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
 105         /* H23 : WWAN_SAR_DETECT_ODL */
 106         PAD_CFG_GPO(GPP_H23, 1, DEEP),
 107
 108         /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
 109         /* BT_I2S_BCLK */
 110         PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
 111         /* BT_I2S_SYNC */
 112         PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
 113         /* BT_I2S_SDO */
 114         PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
 115         /* BT_I2S_SDI */
 116         PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
 117         /* SSP2_SCLK */
 118         PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
 119         /* SSP2_SFRM */
 120         PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
 121         /* SSP_TXD */
 122         PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
 123         /* SSP_RXD */
 124         PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
 125 };
 126
 127 /* Early pad configuration in bootblock for nivviks */
 128 static const struct pad_config early_gpio_table[] = {
 129         /* F12 : GSXDOUT ==> WWAN_RST_L */
 130         PAD_CFG_GPO(GPP_F12, 0, DEEP),
 131         /* H12 : UART0_RTS# ==> SD_PERST_L */
 132         PAD_CFG_GPO(GPP_H12, 0, DEEP),
 133         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 134         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 135         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
 136         PAD_CFG_GPO(GPP_D6, 1, DEEP),
 137         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 138         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 139         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 140         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 141         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 142         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 143         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 144         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 145         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
 146         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 147         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 148         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 149         /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
 150         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 151 };
 152
 153 /* Early pad configuration in bootblock for nirwen */
 154 static const struct pad_config early_gpio_table_nirwen[] = {
 155         /* B4  : SSD_PERST_L */
 156         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 157         /* F12 : GSXDOUT ==> WWAN_RST_L */
 158         PAD_CFG_GPO(GPP_F12, 0, DEEP),
 159         /* H12 : UART0_RTS# ==> SD_PERST_L */
 160         PAD_CFG_GPO(GPP_H12, 0, DEEP),
 161         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 162         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 163         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 164         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 165         /* E13  : SRCCLKREQ1# ==> WWAN_EN */
 166         PAD_CFG_GPO(GPP_E13, 1, DEEP),
 167         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 168         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 169         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 170         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 171         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 172         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 173         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
 174         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 175         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 176         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 177         /* D11 : EN_PP3300_SSD */
 178         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 179         /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
 180         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 181 };
 182
 183 static const struct pad_config romstage_gpio_table[] = {
 184         /* B4  : SSD_PERST_L */
 185         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 186
 187         /* Enable touchscreen, hold in reset */
 188         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 189         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 190         /* C1  : SMBDATA ==> USI_RST_L */
 191         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 192
 193         /* H12 : UART0_RTS# ==> SD_PERST_L */
 194         PAD_CFG_GPO(GPP_H12, 1, DEEP),
 195 };
 196
 197 const struct pad_config *variant_gpio_override_table(size_t *num)
 198 {
 199         const uint32_t id = board_id();
 200         if (id == BOARD_ID_UNKNOWN || id == 0) {
 201                 *num = ARRAY_SIZE(board_id0_overrides);
 202                 return board_id0_overrides;
 203         }
 204
 205         if (id == 1) {
 206                 *num = ARRAY_SIZE(override_gpio_table);
 207                 return override_gpio_table;
 208         }
 209
 210         /* board_id >= 2 means nirwen */
 211         *num = ARRAY_SIZE(override_gpio_table_nirwen);
 212         return override_gpio_table_nirwen;
 213 }
 214
 215 const struct pad_config *variant_early_gpio_table(size_t *num)
 216 {
 217         const uint32_t id = board_id();
 218         if (id == BOARD_ID_UNKNOWN || id < 2) {
 219                 *num = ARRAY_SIZE(early_gpio_table);
 220                 return early_gpio_table;
 221         }
 222
 223         /* board_id >= 2 means nirwen */
 224         *num = ARRAY_SIZE(early_gpio_table_nirwen);
 225         return early_gpio_table_nirwen;
 226 }
 227
 228
 229 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 230 {
 231         *num = ARRAY_SIZE(romstage_gpio_table);
 232         return romstage_gpio_table;
 233 }