src/mainboard/google/brya/variants/pujjoga/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <soc/gpio.h>
   6
   7 /* Pad configuration in ramstage for Sundance */
   8 static const struct pad_config override_gpio_table[] = {
   9         /* A8  : WWAN_RF_DISABLE_ODL */
  10         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  11         /* A18  : HDMI_HPD */
  12         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  13         /* A20  : NC */
  14         PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
  15         /* B5  : SOC_I2C_SUB_SDA */
  16         PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
  17         /* B6  : SOC_I2C_SUB_SCL */
  18         PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
  19         /* C1  : SMBDATA ==> USI_RST_L */
  20         PAD_CFG_GPO(GPP_C1, 1, DEEP),
  21         /* D3  : test point */
  22         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  23         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  24         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  25         /* D8  : NC */
  26         PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
  27         /* D15  : WWAN_SAR_DETECT_2_ODL */
  28         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  29         /* D16  : NC */
  30         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  31         /* D17 : NC ==> SD_WAKE_N */
  32         PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  33         /* E20  : NC */
  34         PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
  35         /* E21  : NC */
  36         PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
  37         /* F12 : WWAN_RST_L */
  38         PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
  39         /* H12  : NC */
  40         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
  41         /* H13  : NC */
  42         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
  43         /* H15  : DDPB_CTRLCLK */
  44         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
  45         /* H17  : DDPB_CTRLDATA */
  46         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
  47         /* H19 : SOC_I2C_SUB_INT_ODL */
  48         PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
  49         /* H21  : WWAN_PERST_L */
  50         PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG),
  51         /* H22  : WCAM_MCLK_R ==> NC */
  52         PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG),
  53         /* H23 : WWAN_SAR_DETECT_ODL ==> NC */
  54         PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG),
  55 };
  56
  57 /* Early pad configuration in bootblock */
  58 static const struct pad_config early_gpio_table[] = {
  59         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
  60         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  61         /*
  62         * WWAN_EN is asserted in ramstage to meet the 500 ms warm reset toff
  63         * requirement. WWAN_EN must be asserted before WWAN_RST_L is released
  64         * (with min delay 0 ms), so this works as long as the pin used for
  65         * WWAN_EN comes before the pin used for WWAN_RST_L.
  66         */
  67         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  68         PAD_CFG_GPO(GPP_D6, 0, DEEP),
  69         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
  70         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
  71         /* F12 : WWAN_RST_L */
  72         PAD_CFG_GPO(GPP_F12, 0, DEEP),
  73         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
  74         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
  75         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
  76         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
  77         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
  78         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
  79         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
  80         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
  81         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
  82         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
  83 };
  84
  85 /* Pad configuration in romstage for Sundance */
  86 static const struct pad_config romstage_gpio_table[] = {
  87         /* Enable touchscreen, hold in reset */
  88         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
  89         PAD_CFG_GPO(GPP_C0, 1, DEEP),
  90         /* C1  : SMBDATA ==> USI_RST_L */
  91         PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP),
  92 };
  93
  94 const struct pad_config *variant_gpio_override_table(size_t *num)
  95 {
  96         *num = ARRAY_SIZE(override_gpio_table);
  97         return override_gpio_table;
  98 }
  99
 100 const struct pad_config *variant_early_gpio_table(size_t *num)
 101 {
 102         *num = ARRAY_SIZE(early_gpio_table);
 103         return early_gpio_table;
 104 }
 105
 106 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 107 {
 108         *num = ARRAY_SIZE(romstage_gpio_table);
 109         return romstage_gpio_table;
 110 }