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mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support
[coreboot.git] / src / mainboard / google / brya / variants / pujjoga / overridetree.cb
blobe1ac962c9fe4d51c47873f562acf91ea9137429f
1 fw_config
2 field WWAN 3 4
3 option WWAN_ABSENT 0
4 option LTE_PRESENT 1
5 option 5G_PRESENT 2
6 end
7 field WIFI_SAR_ID 13 16
8 option WIFI_SAR_TABLE_AX211 0
9 option WIFI_SAR_TABLE_AX203 1
10 end
11 end
12
13 chip soc/intel/alderlake
14 # Acoustic settings
15 register "acoustic_noise_mitigation" = "true"
16 register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
17 register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
18 register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
19 register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
20 register "PreWake" = "100"
21
22 register "sagv" = "SaGv_Enabled"
23
24 # EMMC Tx CMD Delay
25 # Refer to EDS-Vol2-42.3.7.
26 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
27 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
28 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
29
30 # EMMC TX DATA Delay 1
31 # Refer to EDS-Vol2-42.3.8.
32 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
33 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
34 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
35
36 # EMMC TX DATA Delay 2
37 # Refer to EDS-Vol2-42.3.9.
38 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
39 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
40 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
41 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
42 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
43
44 # EMMC RX CMD/DATA Delay 1
45 # Refer to EDS-Vol2-42.3.10.
46 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
47 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
48 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
49 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
50 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
51
52 # EMMC RX CMD/DATA Delay 2
53 # Refer to EDS-Vol2-42.3.12.
54 # [17:16] stands for Rx Clock before Output Buffer,
55 # 00: Rx clock after output buffer,
56 # 01: Rx clock before output buffer,
57 # 10: Automatic selection based on working mode.
58 # 11: Reserved
59 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
60 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
61 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023"
62
63 # EMMC Rx Strobe Delay
64 # Refer to EDS-Vol2-42.3.11.
65 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
66 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
67 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"
68
69 # SOC Aux orientation override:
70 # This is a bitfield that corresponds to up to 4 TCSS ports.
71 # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
72 # TcssAuxOri = 0101b
73 # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
74 # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
75 # motherboard to USBC connector
76 register "tcss_aux_ori" = "5"
77
78 register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
79 register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
80
81 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
82 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
83 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB-A1
84 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
85 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera
86 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera
87 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
88 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
89
90 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN
91
92 # Configure external V1P05/Vnn/VnnSx Rails for Pujjoga
93 register "ext_fivr_settings" = "{
94 .configure_ext_fivr = 1,
95 }"
96
97 # Intel Common SoC Config
98 #+-------------------+---------------------------+
99 #| Field | Value |
100 #+-------------------+---------------------------+
101 #| I2C0 | TPM. Early init is |
102 #| | required to set up a BAR |
103 #| | for TPM communication |
104 #| I2C1 | Touchscreen |
105 #| I2C2 | Sub-board(PSensor)/WCAM |
106 #| I2C3 | Audio |
107 #| I2C5 | Trackpad |
108 #+-------------------+---------------------------+
109 register "common_soc_config" = "{
110 .i2c[0] = {
111 .early_init = 1,
112 .speed = I2C_SPEED_FAST_PLUS,
113 .speed_config[0] = {
114 .speed = I2C_SPEED_FAST_PLUS,
115 .scl_lcnt = 55,
116 .scl_hcnt = 30,
117 .sda_hold = 7,
118 }
119 },
120 .i2c[1] = {
121 .speed = I2C_SPEED_FAST,
122 .speed_config[0] = {
123 .speed = I2C_SPEED_FAST,
124 .scl_lcnt = 157,
125 .scl_hcnt = 79,
126 .sda_hold = 7,
127 }
128 },
129 .i2c[2] = {
130 .speed = I2C_SPEED_FAST,
131 .speed_config[0] = {
132 .speed = I2C_SPEED_FAST,
133 .scl_lcnt = 157,
134 .scl_hcnt = 79,
135 .sda_hold = 7,
136 }
137 },
138 .i2c[3] = {
139 .speed = I2C_SPEED_FAST,
140 .speed_config[0] = {
141 .speed = I2C_SPEED_FAST,
142 .scl_lcnt = 158,
143 .scl_hcnt = 79,
144 .sda_hold = 7,
145 }
146 },
147 .i2c[5] = {
148 .speed = I2C_SPEED_FAST,
149 .speed_config[0] = {
150 .speed = I2C_SPEED_FAST,
151 .scl_lcnt = 158,
152 .scl_hcnt = 79,
153 .sda_hold = 7,
154 }
155 },
156 }"
157
158 device domain 0 on
159 device ref dtt on
160 chip drivers/intel/dptf
161 ## sensor information
162 register "options.tsr[0].desc" = ""CPU""
163 register "options.tsr[1].desc" = ""DDR""
164 register "options.tsr[2].desc" = ""5VCharger""
165
166
167 ## Passive Policy
168 register "policies.passive" = "{
169 [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000),
170 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
171 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 60000),
172 [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 15000),
173 }"
174
175 ## Critical Policy
176 register "policies.critical" = "{
177 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
178 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN),
179 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
180 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN),
181 }"
182
183 register "controls.power_limits" = "{
184 .pl1 = {
185 .min_power = 3000,
186 .max_power = 6000,
187 .time_window_min = 1 * MSECS_PER_SEC,
188 .time_window_max = 1 * MSECS_PER_SEC,
189 .granularity = 200,
190 },
191 .pl2 = {
192 .min_power = 25000,
193 .max_power = 25000,
194 .time_window_min = 1 * MSECS_PER_SEC,
195 .time_window_max = 1 * MSECS_PER_SEC,
196 .granularity = 1000,
197 }
198 }"
199
200 ## Charger Performance Control (Control, mA)
201 register "controls.charger_perf" = "{
202 [0] = { 255, 3000 },
203 [1] = { 24, 2000 },
204 [2] = { 16, 1500 },
205 [3] = { 8, 1000 }
206 }"
207 device generic 0 on end
208 end
209 end
210 device ref i2c1 on
211 chip drivers/i2c/hid
212 register "generic.hid" = ""GDIX0000""
213 register "generic.desc" = ""Goodix Touchscreen""
214 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
215 register "generic.detect" = "1"
216 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
217 register "generic.enable_delay_ms" = "20"
218 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
219 register "generic.reset_delay_ms" = "180"
220 register "generic.reset_off_delay_ms" = "3"
221 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
222 register "generic.stop_off_delay_ms" = "1"
223 register "generic.has_power_resource" = "1"
224 register "hid_desc_reg_offset" = "0x01"
225 device i2c 5d on end
226 end
227 chip drivers/generic/gpio_keys
228 register "name" = ""PENH""
229 register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
230 register "key.wake_gpe" = "GPE0_DW2_15"
231 register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
232 register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
233 register "key.dev_name" = ""EJCT""
234 register "key.linux_code" = "SW_PEN_INSERTED"
235 register "key.linux_input_type" = "EV_SW"
236 register "key.label" = ""pen_eject""
237 device generic 0 on end
238 end
239 end
240 device ref i2c2 on
241 chip drivers/i2c/sx9324
242 register "desc" = ""SAR Proximity Sensor""
243 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
244 register "speed" = "I2C_SPEED_FAST"
245 register "uid" = "1"
246 register "reg_gnrl_ctrl0" = "0x16"
247 register "reg_gnrl_ctrl1" = "0x21"
248 register "reg_afe_ctrl0" = "0x00"
249 register "reg_afe_ctrl1" = "0x10"
250 register "reg_afe_ctrl2" = "0x00"
251 register "reg_afe_ctrl3" = "0x00"
252 register "reg_afe_ctrl4" = "0x47"
253 register "reg_afe_ctrl5" = "0x00"
254 register "reg_afe_ctrl6" = "0x00"
255 register "reg_afe_ctrl7" = "0x47"
256 register "reg_afe_ctrl8" = "0x12"
257 register "reg_afe_ctrl9" = "0x08"
258 register "reg_afe_ph0" = "0x3d"
259 register "reg_afe_ph1" = "0x1b"
260 register "reg_afe_ph2" = "0x1f"
261 register "reg_afe_ph3" = "0x3d"
262 register "reg_prox_ctrl0" = "0x0b"
263 register "reg_prox_ctrl1" = "0x0a"
264 register "reg_prox_ctrl2" = "0x90"
265 register "reg_prox_ctrl3" = "0x60"
266 register "reg_prox_ctrl4" = "0x0c"
267 register "reg_prox_ctrl5" = "0x00"
268 register "reg_prox_ctrl6" = "0x19"
269 register "reg_prox_ctrl7" = "0x58"
270 register "reg_adv_ctrl0" = "0x00"
271 register "reg_adv_ctrl1" = "0x00"
272 register "reg_adv_ctrl2" = "0x00"
273 register "reg_adv_ctrl3" = "0x00"
274 register "reg_adv_ctrl4" = "0x00"
275 register "reg_adv_ctrl5" = "0x05"
276 register "reg_adv_ctrl6" = "0x00"
277 register "reg_adv_ctrl7" = "0x00"
278 register "reg_adv_ctrl8" = "0x00"
279 register "reg_adv_ctrl9" = "0x00"
280 register "reg_adv_ctrl10" = "0x00"
281 register "reg_adv_ctrl11" = "0x00"
282 register "reg_adv_ctrl12" = "0x00"
283 register "reg_adv_ctrl13" = "0x00"
284 register "reg_adv_ctrl14" = "0x80"
285 register "reg_adv_ctrl15" = "0x0c"
286 register "reg_adv_ctrl16" = "0x08"
287 register "reg_adv_ctrl17" = "0x56"
288 register "reg_adv_ctrl18" = "0x33"
289 register "reg_adv_ctrl19" = "0x00"
290 register "reg_adv_ctrl20" = "0x00"
291
292 register "ph0_pin" = "{1, 3, 3}"
293 register "ph1_pin" = "{3, 2, 1}"
294 register "ph2_pin" = "{3, 3, 1}"
295 register "ph3_pin" = "{1, 3, 3}"
296 register "ph01_resolution" = "1024"
297 register "ph23_resolution" = "1024"
298 register "startup_sensor" = "1"
299 register "ph01_proxraw_strength" = "3"
300 register "ph23_proxraw_strength" = "2"
301 register "avg_pos_strength" = "256"
302 register "cs_idle_sleep" = ""hi-z""
303 register "int_comp_resistor" = ""lowest""
304 register "input_precharge_resistor_ohms" = "4000"
305 register "input_analog_gain" = "1"
306 device i2c 28 on
307 probe WWAN LTE_PRESENT
308 end
309 end
310 end
311 device ref i2c3 on
312 chip drivers/i2c/generic
313 register "hid" = ""RTL5682""
314 register "name" = ""RT58""
315 register "desc" = ""Headset Codec""
316 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
317 # Set the jd_src to RT5668_JD1 for jack detection
318 register "property_count" = "1"
319 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
320 register "property_list[0].name" = ""realtek,jd-src""
321 register "property_list[0].integer" = "1"
322 device i2c 1a on end
323 end
324 chip drivers/generic/alc1015
325 register "hid" = ""RTL1019""
326 register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
327 device generic 0 on end
328 end
329 end
330 device ref i2c5 on
331 chip drivers/i2c/generic
332 register "hid" = ""ELAN0000""
333 register "desc" = ""ELAN Touchpad""
334 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
335 register "wake" = "GPE0_DW2_14"
336 register "detect" = "1"
337 device i2c 15 on end
338 end
339 chip drivers/i2c/hid
340 register "generic.hid" = ""SYNA0000""
341 register "generic.cid" = ""ACPI0C50""
342 register "generic.desc" = ""Synaptics Touchpad""
343 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
344 register "generic.wake" = "GPE0_DW2_14"
345 register "generic.detect" = "1"
346 register "hid_desc_reg_offset" = "0x20"
347 device i2c 0x2c on end
348 end
349 end
350 device ref pcie_rp4 on
351 # PCIe 4 WLAN
352 register "pch_pcie_rp[PCH_RP(4)]" = "{
353 .clk_src = 2,
354 .clk_req = 2,
355 .flags = PCIE_RP_LTR | PCIE_RP_AER,
356 }"
357 chip drivers/wifi/generic
358 register "wake" = "GPE0_DW1_03"
359 register "add_acpi_dma_property" = "true"
360 device pci 00.0 on end
361 end
362 end
363 device ref pcie_rp7 off end
364 device ref pch_espi on
365 chip ec/google/chromeec
366 use conn0 as mux_conn[0]
367 use conn1 as mux_conn[1]
368 device pnp 0c09.0 on end
369 end
370 end
371 device ref pmc hidden
372 chip drivers/intel/pmc_mux
373 device generic 0 on
374 chip drivers/intel/pmc_mux/conn
375 use usb2_port1 as usb2_port
376 use tcss_usb3_port1 as usb3_port
377 device generic 0 alias conn0 on end
378 end
379 chip drivers/intel/pmc_mux/conn
380 use usb2_port2 as usb2_port
381 use tcss_usb3_port2 as usb3_port
382 device generic 1 alias conn1 on end
383 end
384 end
385 end
386 end
387 device ref tcss_xhci on
388 chip drivers/usb/acpi
389 device ref tcss_root_hub on
390 chip drivers/usb/acpi
391 register "desc" = ""USB3 Type-C Port C0 (MLB)""
392 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
393 register "use_custom_pld" = "true"
394 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
395 device ref tcss_usb3_port1 on end
396 end
397 chip drivers/usb/acpi
398 register "desc" = ""USB3 Type-C Port C1 (MLB)""
399 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
400 register "use_custom_pld" = "true"
401 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
402 device ref tcss_usb3_port2 on end
403 end
404 end
405 end
406 end
407 device ref xhci on
408 chip drivers/usb/acpi
409 device ref xhci_root_hub on
410 chip drivers/usb/acpi
411 register "desc" = ""USB2 Type-C Port C0 (MLB)""
412 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
413 register "use_custom_pld" = "true"
414 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
415 device ref usb2_port1 on end
416 end
417 chip drivers/usb/acpi
418 register "desc" = ""USB2 Type-C Port C1 (MLB)""
419 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
420 register "use_custom_pld" = "true"
421 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
422 device ref usb2_port2 on end
423
424 end
425 chip drivers/usb/acpi
426 register "desc" = ""USB2 Type-A Port A1 (DB)""
427 register "type" = "UPC_TYPE_A"
428 register "use_custom_pld" = "true"
429 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
430 device ref usb2_port4 on end
431 end
432
433 chip drivers/usb/acpi
434 register "desc" = ""USB2 WWAN""
435 register "type" = "UPC_TYPE_INTERNAL"
436 device ref usb2_port5 on
437 probe WWAN LTE_PRESENT
438 end
439 end
440 chip drivers/usb/acpi
441 register "desc" = ""USB2 UFC""
442 register "type" = "UPC_TYPE_INTERNAL"
443 device ref usb2_port6 on end
444 end
445 chip drivers/usb/acpi
446 register "desc" = ""USB2 WFC""
447 register "type" = "UPC_TYPE_INTERNAL"
448 device ref usb2_port7 on end
449 end
450 chip drivers/usb/acpi
451 register "desc" = ""USB2 Bluetooth""
452 register "type" = "UPC_TYPE_INTERNAL"
453 register "reset_gpio" =
454 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
455 device ref usb2_port8 on end
456 end
457 chip drivers/usb/acpi
458 register "desc" = ""CNVi Bluetooth""
459 register "type" = "UPC_TYPE_INTERNAL"
460 register "reset_gpio" =
461 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
462 device ref usb2_port10 on end
463 end
464 chip drivers/usb/acpi
465 register "desc" = ""USB3 Type-A Port A1 (DB)""
466 register "type" = "UPC_TYPE_USB3_A"
467 register "use_custom_pld" = "true"
468 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
469 device ref usb3_port2 on end
470 end
471 chip drivers/usb/acpi
472 register "desc" = ""USB3 WWAN""
473 register "type" = "UPC_TYPE_INTERNAL"
474 device ref usb3_port3 on
475 probe WWAN LTE_PRESENT
476 end
477 end
478 end
479 end
480 end
481 end
482 end
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