src/mainboard/google/brya/variants/taeko/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <console/console.h>
   6 #include <gpio.h>
   7 #include <memory_info.h>
   8 #include <string.h>
   9
  10 static const struct mb_cfg baseboard_memcfg = {
  11         .type = MEM_TYPE_LP4X,
  12
  13         .rcomp = {
  14                 /* Baseboard uses only 100ohm Rcomp resistors */
  15                 .resistor = 100,
  16
  17                 /* Baseboard Rcomp target values */
  18                 .targets = {40, 30, 30, 30, 30},
  19         },
  20
  21         /* DQ byte map */
  22         .lpx_dq_map = {
  23                 .ddr0 = {
  24                         .dq0 = {  9, 11,  8, 10, 12, 14, 13, 15, },
  25                         .dq1 = {  4,  7,  6,  5,  2,  3,  0,  1, },
  26                 },
  27                 .ddr1 = {
  28                         .dq0 = { 15, 12, 14, 13,  9, 10, 11,  8, },
  29                         .dq1 = {  0,  1,  3,  2,  7,  5,  4,  6, },
  30                 },
  31                 .ddr2 = {
  32                         .dq0 = {  2,  3,  1,  0,  6,  7,  5,  4, },
  33                         .dq1 = { 15,  9, 14,  8, 11, 10, 13, 12, },
  34                 },
  35                 .ddr3 = {
  36                         .dq0 = {  3,  1,  2,  0,  4,  6,  7,  5, },
  37                         .dq1 = { 13, 15, 14, 12, 11,  9,  8, 10, },
  38                 },
  39                 .ddr4 = {
  40                         .dq0 = { 13, 12, 14, 15,  9,  8, 10, 11, },
  41                         .dq1 = {  4,  7,  5,  6,  1,  2,  0,  3, },
  42                 },
  43                 .ddr5 = {
  44                         .dq0 = {  5,  0,  6,  4,  3,  1,  7,  2, },
  45                         .dq1 = { 11,  9, 10,  8, 15, 12, 14, 13, },
  46                 },
  47                 .ddr6 = {
  48                         .dq0 = { 15, 12, 14, 13, 10,  9, 11,  8, },
  49                         .dq1 = {  0,  1,  2,  3,  5,  6,  4,  7, },
  50                 },
  51                 .ddr7 = {
  52                         .dq0 = {  0,  3,  1,  2,  4,  5,  6,  7, },
  53                         .dq1 = { 11,  8, 13, 14,  9, 12, 15, 10, },
  54                 },
  55         },
  56
  57         /* DQS CPU<>DRAM map */
  58         .lpx_dqs_map = {
  59                 .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
  60                 .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
  61                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
  62                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
  63                 .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
  64                 .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
  65                 .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
  66                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
  67         },
  68
  69         .LpDdrDqDqsReTraining = 1,
  70
  71         .ect = 1, /* Enable Early Command Training */
  72 };
  73
  74 static const struct mb_cfg hynix_memconfig = {
  75         .type = MEM_TYPE_LP4X,
  76
  77         .rcomp = {
  78                 /* Baseboard uses only 100ohm Rcomp resistors */
  79                 .resistor = 100,
  80
  81                 /* Baseboard Rcomp target values */
  82                 .targets = {40, 30, 30, 30, 30},
  83         },
  84
  85         /* DQ byte map */
  86         .lpx_dq_map = {
  87                 .ddr0 = {
  88                         .dq0 = {  9, 11,  8, 10, 12, 14, 13, 15, },
  89                         .dq1 = {  4,  7,  6,  5,  2,  3,  0,  1, },
  90                 },
  91                 .ddr1 = {
  92                         .dq0 = { 15, 12, 14, 13,  9, 10, 11,  8, },
  93                         .dq1 = {  0,  1,  3,  2,  7,  5,  4,  6, },
  94                 },
  95                 .ddr2 = {
  96                         .dq0 = {  2,  3,  1,  0,  6,  7,  5,  4, },
  97                         .dq1 = { 15,  9, 14,  8, 11, 10, 13, 12, },
  98                 },
  99                 .ddr3 = {
 100                         .dq0 = {  3,  1,  2,  0,  4,  6,  7,  5, },
 101                         .dq1 = { 13, 15, 14, 12, 11,  9,  8, 10, },
 102                 },
 103                 .ddr4 = {
 104                         .dq0 = { 13, 12, 14, 15,  9,  8, 10, 11, },
 105                         .dq1 = {  4,  7,  5,  6,  1,  2,  0,  3, },
 106                 },
 107                 .ddr5 = {
 108                         .dq0 = {  5,  0,  6,  4,  3,  1,  7,  2, },
 109                         .dq1 = { 11,  9, 10,  8, 15, 12, 14, 13, },
 110                 },
 111                 .ddr6 = {
 112                         .dq0 = { 15, 12, 14, 13, 10,  9, 11,  8, },
 113                         .dq1 = {  0,  1,  2,  3,  5,  6,  4,  7, },
 114                 },
 115                 .ddr7 = {
 116                         .dq0 = {  0,  3,  1,  2,  4,  5,  6,  7, },
 117                         .dq1 = { 11,  8, 13, 14,  9, 12, 15, 10, },
 118                 },
 119         },
 120
 121         /* DQS CPU<>DRAM map */
 122         .lpx_dqs_map = {
 123                 .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
 124                 .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
 125                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
 126                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
 127                 .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
 128                 .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
 129                 .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
 130                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
 131         },
 132
 133         .LpDdrDqDqsReTraining = 1,
 134
 135         .ect = 1, /* Enable Early Command Training */
 136
 137         .cs_pi_start_high_in_ect = 1,
 138 };
 139 const struct mb_cfg *variant_memory_params(void)
 140 {
 141         const char *dram_part_num = mainboard_get_dram_part_num();
 142         if (dram_part_num) {
 143                 if (strcmp(dram_part_num, "H54G46CYRBX267N") == 0) {
 144                         printk(BIOS_INFO, "Enable cs_pi_start_high_in_ect for Hynix DRAM part\n");
 145                         return &hynix_memconfig;
 146                 }
 147         }
 148         return &baseboard_memcfg;
 149 }
 150
 151 int variant_memory_sku(void)
 152 {
 153         /*
 154          * Memory configuration board straps
 155          * GPIO_MEM_CONFIG_0    GPP_E11
 156          * GPIO_MEM_CONFIG_1    GPP_E2
 157          * GPIO_MEM_CONFIG_2    GPP_E1
 158          * GPIO_MEM_CONFIG_3    GPP_E12
 159          */
 160         gpio_t spd_gpios[] = {
 161                 GPP_E11,
 162                 GPP_E2,
 163                 GPP_E1,
 164                 GPP_E12,
 165         };
 166
 167         return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 168 }
 169
 170 bool variant_is_half_populated(void)
 171 {
 172         /* GPIO_MEM_CH_SEL GPP_E13 */
 173         return gpio_get(GPP_E13);
 174 }