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mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support
[coreboot.git] / src / mainboard / google / brya / variants / taeko / overridetree.cb
blob964d83309b6e04988800f73db4429fbcb149fdcc
1 fw_config
2 field DB_USB 0 1
3 option DB_USB_ABSENT 0
4 option DB_USB3_NO_A 1
5 option DB_USB3_1C_1A 2
6 end
7 field DB_SD 2 3
8 option DB_SD_ABSENT 0
9 option DB_SD_OZ711LV2LN 1
10 end
11 field KB_BL 4
12 option KB_BL_ABSENT 0
13 option KB_BL_PRESENT 1
14 end
15 field AUDIO 5 7
16 option AUDIO_UNKNOWN 0
17 option AUDIO_MAX98357_ALC5682I_I2S 1
18 option AUDIO_MAX98357_ALC5682I_VS_I2S 2
19 end
20 field KB_LAYOUT 8 9
21 option KB_LAYOUT_DEFAULT 0
22 end
23 field WIFI_SAR_ID 10 11
24 option WIFI_SAR_ID_0 0
25 option WIFI_SAR_ID_1 1
26 option WIFI_SAR_ID_2 2
27 option WIFI_SAR_ID_3 3
28 end
29 field BOOT_NVME_MASK 12
30 option BOOT_NVME_DISABLED 0
31 option BOOT_NVME_ENABLED 1
32 end
33 field BOOT_EMMC_MASK 13
34 option BOOT_EMMC_DISABLED 0
35 option BOOT_EMMC_ENABLED 1
36 end
37 field THERMAL 16
38 option THERMAL_FAN_TABLE_0 0
39 option THERMAL_FAN_TABLE_1 1
40 end
41 field HPS 17
42 option HPS_ABSENT 0
43 option HPS_PRESENT 1
44 end
45 end
46 chip soc/intel/alderlake
47 register "domain_vr_config[VR_DOMAIN_IA]" = "{
48 .enable_fast_vmode = 1,
49 }"
50
51 # As per Intel Advisory doc#723158, the change is required to prevent possible
52 # display flickering issue.
53 register "usb2_phy_sus_pg_disable" = "1"
54
55 # Acoustic settings
56 register "acoustic_noise_mitigation" = "true"
57 register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
58 register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
59 register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
60 register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
61 register "PreWake" = "100"
62 register "ext_fivr_settings" = "{
63 .configure_ext_fivr = 1,
64 .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
65 .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
66 .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
67 FIVR_VOLTAGE_MIN_ACTIVE |
68 FIVR_VOLTAGE_MIN_RETENTION,
69 .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
70 FIVR_VOLTAGE_MIN_ACTIVE |
71 FIVR_VOLTAGE_MIN_RETENTION,
72 .v1p05_icc_max_ma = 500,
73 .vnn_sx_voltage_mv = 1250,
74 }"
75 register "tcss_aux_ori" = "1"
76 register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
77 register "sagv" = "SaGv_Enabled"
78
79 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1
80 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1
81 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
82 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # DB Type-A Port A1
83
84 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A1
85 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
86
87 # Intel Common SoC Config
88 #+-------------------+---------------------------+
89 #| Field | Value |
90 #+-------------------+---------------------------+
91 #| GSPI1 | Fingerprint MCU |
92 #| I2C0 | Audio |
93 #| I2C1 | cr50 TPM. Early init is |
94 #| | required to set up a BAR |
95 #| | for TPM communication |
96 #| I2C2 | HPS |
97 #| I2C3 | Touchscreen |
98 #| I2C5 | Trackpad |
99 #+-------------------+---------------------------+
100 register "common_soc_config" = "{
101 .i2c[0] = {
102 .speed = I2C_SPEED_FAST,
103 },
104 .i2c[1] = {
105 .early_init = 1,
106 .speed = I2C_SPEED_FAST,
107 .rise_time_ns = 600,
108 .fall_time_ns = 400,
109 .data_hold_time_ns = 50,
110 },
111 .i2c[2] = {
112 .speed = I2C_SPEED_FAST,
113 },
114 .i2c[3] = {
115 .early_init = 1,
116 .speed = I2C_SPEED_FAST,
117 },
118 .i2c[5] = {
119 .rise_time_ns = 650,
120 .fall_time_ns = 400,
121 .data_hold_time_ns = 500,
122 .speed_config[0] = {
123 .speed = I2C_SPEED_FAST,
124 .scl_lcnt = 160,
125 .scl_hcnt = 70,
126 .sda_hold = 40,
127 }
128 },
129 }"
130 # I2C Port Config
131 register "serial_io_i2c_mode" = "{
132 [PchSerialIoIndexI2C0] = PchSerialIoPci,
133 [PchSerialIoIndexI2C1] = PchSerialIoPci,
134 [PchSerialIoIndexI2C2] = PchSerialIoPci,
135 [PchSerialIoIndexI2C3] = PchSerialIoPci,
136 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
137 [PchSerialIoIndexI2C5] = PchSerialIoPci,
138 }"
139 device domain 0 on
140 device ref igpu on
141 chip drivers/gfx/generic
142 register "device_count" = "3"
143 # DDIA for eDP
144 register "device[0].name" = ""LCD0""
145 # Internal panel on the first port of the graphics chip
146 register "device[0].type" = "panel"
147 # DDIB is unused and HDMI is not enumerated in the kernel, so no GFX device is added for DDIB
148 # TCP0 (DP-1) for port C0
149 register "device[1].name" = ""DD01""
150 register "device[1].use_pld" = "true"
151 register "device[1].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
152 # TCP1 is unused and not enumerated in the kernel, so no GFX device is added for TCP1
153 # TCP2 (DP-2) for port C1
154 register "device[2].name" = ""DD02""
155 register "device[2].use_pld" = "true"
156 register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
157 # TCP3 is unused and not enumerated in the kernel, so no GFX device is added for TCP3
158 device generic 0 on end
159 end
160 end # Integrated Graphics Device
161 device ref dtt on
162 chip drivers/intel/dptf
163 ## sensor information
164 register "options.tsr[0].desc" = ""DRAM_SOC""
165 register "options.tsr[1].desc" = ""Ambient""
166 register "options.tsr[2].desc" = ""Charger""
167 register "options.tsr[3].desc" = ""WWAN""
168
169 # TODO: below values are initial reference values only
170 ## Active Policy
171 register "policies.active" = "{
172 [0] = {
173 .target = DPTF_CPU,
174 .thresholds = {
175 TEMP_PCT(85, 90),
176 TEMP_PCT(80, 74),
177 TEMP_PCT(75, 74),
178 TEMP_PCT(70, 74),
179 TEMP_PCT(65, 74),
180 }
181 },
182 [1] = {
183 .target = DPTF_TEMP_SENSOR_1,
184 .thresholds = {
185 TEMP_PCT(50, 70),
186 TEMP_PCT(47, 58),
187 TEMP_PCT(45, 47),
188 TEMP_PCT(42, 45),
189 TEMP_PCT(39, 39),
190 }
191 },
192 [2] = {
193 .target = DPTF_TEMP_SENSOR_2,
194 .thresholds = {
195 TEMP_PCT(50, 70),
196 TEMP_PCT(47, 58),
197 TEMP_PCT(45, 47),
198 TEMP_PCT(42, 45),
199 TEMP_PCT(39, 39),
200 }
201 },
202 [3] = {
203 .target = DPTF_TEMP_SENSOR_3,
204 .thresholds = {
205 TEMP_PCT(50, 70),
206 TEMP_PCT(47, 58),
207 TEMP_PCT(45, 47),
208 TEMP_PCT(42, 45),
209 TEMP_PCT(39, 39),
210 }
211 }
212 }"
213
214 ## Passive Policy
215 register "policies.passive" = "{
216 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
217 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000),
218 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000),
219 [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000),
220 [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000),
221 }"
222
223 ## Critical Policy
224 register "policies.critical" = "{
225 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
226 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN),
227 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
228 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN),
229 [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN),
230 }"
231
232 register "controls.power_limits" = "{
233 .pl1 = {
234 .min_power = 3000,
235 .max_power = 15000,
236 .time_window_min = 28 * MSECS_PER_SEC,
237 .time_window_max = 32 * MSECS_PER_SEC,
238 .granularity = 200,
239 },
240 .pl2 = {
241 .min_power = 55000,
242 .max_power = 55000,
243 .time_window_min = 28 * MSECS_PER_SEC,
244 .time_window_max = 32 * MSECS_PER_SEC,
245 .granularity = 1000,
246 }
247 }"
248
249 ## Charger Performance Control (Control, mA)
250 register "controls.charger_perf" = "{
251 [0] = { 255, 1700 },
252 [1] = { 24, 1500 },
253 [2] = { 16, 1000 },
254 [3] = { 8, 500 }
255 }"
256
257 ## Fan Performance Control (Percent, Speed, Noise, Power)
258 register "controls.fan_perf" = "{
259 [0] = { 100, 6000, 220, 2200, },
260 [1] = { 92, 5500, 180, 1800, },
261 [2] = { 85, 5000, 145, 1450, },
262 [3] = { 70, 4400, 115, 1150, },
263 [4] = { 56, 3900, 90, 900, },
264 [5] = { 45, 3300, 55, 550, },
265 [6] = { 38, 3000, 30, 300, },
266 [7] = { 33, 2900, 15, 150, },
267 [8] = { 10, 800, 10, 100, },
268 [9] = { 0, 0, 0, 50, }
269 }"
270
271 ## Fan options
272 register "options.fan.fine_grained_control" = "true"
273 register "options.fan.step_size" = "2"
274
275 device generic 0 on
276 probe THERMAL THERMAL_FAN_TABLE_0
277 end
278 end
279 chip drivers/intel/dptf
280 ## sensor information
281 register "options.tsr[0].desc" = ""DRAM_SOC""
282 register "options.tsr[1].desc" = ""Ambient""
283 register "options.tsr[2].desc" = ""Charger""
284 register "options.tsr[3].desc" = ""WWAN""
285
286 ## Active Policy
287 register "policies.active" = "{
288 [0] = {
289 .target = DPTF_CPU,
290 .thresholds = {
291 TEMP_PCT(60, 68),
292 TEMP_PCT(56, 50),
293 TEMP_PCT(52, 50),
294 TEMP_PCT(46, 40),
295 TEMP_PCT(42, 40),
296 }
297 },
298 [1] = {
299 .target = DPTF_TEMP_SENSOR_1,
300 .thresholds = {
301 TEMP_PCT(60, 68),
302 TEMP_PCT(56, 50),
303 TEMP_PCT(52, 50),
304 TEMP_PCT(46, 40),
305 TEMP_PCT(42, 40),
306 }
307 },
308 [2] = {
309 .target = DPTF_TEMP_SENSOR_2,
310 .thresholds = {
311 TEMP_PCT(60, 68),
312 TEMP_PCT(56, 50),
313 TEMP_PCT(52, 50),
314 TEMP_PCT(46, 40),
315 TEMP_PCT(42, 40),
316 }
317 },
318 [3] = {
319 .target = DPTF_TEMP_SENSOR_3,
320 .thresholds = {
321 TEMP_PCT(60, 68),
322 TEMP_PCT(56, 50),
323 TEMP_PCT(52, 50),
324 TEMP_PCT(46, 40),
325 TEMP_PCT(42, 40),
326 }
327 }
328 }"
329
330 ## Passive Policy
331 register "policies.passive" = "{
332 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
333 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000),
334 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000),
335 [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000),
336 [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000),
337 }"
338
339 ## Critical Policy
340 register "policies.critical" = "{
341 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
342 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN),
343 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
344 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN),
345 [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN),
346 }"
347
348 register "controls.power_limits" = "{
349 .pl1 = {
350 .min_power = 3000,
351 .max_power = 15000,
352 .time_window_min = 28 * MSECS_PER_SEC,
353 .time_window_max = 32 * MSECS_PER_SEC,
354 .granularity = 200,
355 },
356 .pl2 = {
357 .min_power = 55000,
358 .max_power = 55000,
359 .time_window_min = 28 * MSECS_PER_SEC,
360 .time_window_max = 32 * MSECS_PER_SEC,
361 .granularity = 1000,
362 }
363 }"
364
365 ## Charger Performance Control (Control, mA)
366 register "controls.charger_perf" = "{
367 [0] = { 255, 1700 },
368 [1] = { 24, 1500 },
369 [2] = { 16, 1000 },
370 [3] = { 8, 500 }
371 }"
372
373 ## Fan Performance Control (Percent, Speed, Noise, Power)
374 register "controls.fan_perf" = "{
375 [0] = { 100, 6000, 220, 2200, },
376 [1] = { 92, 5500, 180, 1800, },
377 [2] = { 78, 4500, 145, 1450, },
378 [3] = { 68, 3900, 115, 1150, },
379 [4] = { 60, 3600, 90, 900, },
380 [5] = { 50, 3200, 55, 550, },
381 [6] = { 40, 2800, 30, 300, },
382 [7] = { 33, 2500, 15, 150, },
383 [8] = { 12, 800, 10, 100, },
384 [9] = { 0, 0, 0, 50, }
385 }"
386
387 ## Fan options
388 register "options.fan.fine_grained_control" = "true"
389 register "options.fan.step_size" = "2"
390
391 device generic 1 on
392 probe THERMAL THERMAL_FAN_TABLE_1
393 end
394 end
395 end
396 device ref pcie4_0 on
397 # Enable CPU PCIE RP 1 using CLK 0
398 register "cpu_pcie_rp[CPU_RP(1)]" = "{
399 .clk_req = 0,
400 .clk_src = 0,
401 .flags = PCIE_RP_LTR | PCIE_RP_AER,
402 }"
403 probe BOOT_NVME_MASK BOOT_NVME_ENABLED
404 end
405 device ref tbt_pcie_rp0 off end
406 device ref tbt_pcie_rp1 off end
407 device ref tbt_pcie_rp2 off end
408 device ref i2c0 on
409 chip drivers/i2c/generic
410 register "hid" = ""10EC5682""
411 register "name" = ""RT58""
412 register "desc" = ""Headset Codec""
413 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
414 # Set the jd_src to RT5668_JD1 for jack detection
415 register "property_count" = "1"
416 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
417 register "property_list[0].name" = ""realtek,jd-src""
418 register "property_list[0].integer" = "1"
419 device i2c 1a on
420 probe AUDIO AUDIO_MAX98357_ALC5682I_I2S
421 end
422 end
423 chip drivers/i2c/generic
424 register "hid" = ""RTL5682""
425 register "name" = ""RT58""
426 register "desc" = ""Headset Codec""
427 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
428 # Set the jd_src to RT5668_JD1 for jack detection
429 register "property_count" = "1"
430 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
431 register "property_list[0].name" = ""realtek,jd-src""
432 register "property_list[0].integer" = "1"
433 device i2c 1a on
434 probe AUDIO AUDIO_MAX98357_ALC5682I_VS_I2S
435 end
436 end
437 end
438 device ref i2c1 on
439 chip drivers/i2c/tpm
440 register "hid" = ""GOOG0005""
441 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
442 device i2c 50 on end
443 end
444 end
445 device ref i2c2 on
446 chip drivers/i2c/generic
447 register "hid" = ""GOOG0020""
448 register "desc" = ""ChromeOS HPS""
449 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
450 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
451 # HPS uses I2C addresses 0x30 and 0x51.
452 # The address we provide here is not significant because
453 # neither coreboot nor Linux have a driver for HPS,
454 # it's only used from userspace.
455 device i2c 30 on
456 probe HPS HPS_PRESENT
457 end
458 end
459 end
460 device ref i2c3 on
461 chip drivers/i2c/hid
462 register "generic.hid" = ""GDIX0000""
463 register "generic.desc" = ""Goodix Touchscreen""
464 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
465 register "generic.detect" = "1"
466 register "generic.reset_gpio" =
467 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
468 # Parameter T5 >= 180ms
469 register "generic.reset_delay_ms" = "180"
470 # Parameter T2 >= 1ms
471 register "generic.reset_off_delay_ms" = "3"
472 register "generic.enable_gpio" =
473 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
474 # Parameter T1 >= 20ms
475 register "generic.enable_delay_ms" = "20"
476 register "generic.stop_gpio" =
477 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)"
478 # Parameter T4 >= 1ms
479 register "generic.stop_off_delay_ms" = "1"
480 register "generic.has_power_resource" = "1"
481 register "hid_desc_reg_offset" = "0x01"
482 device i2c 5d on end
483 end
484 chip drivers/i2c/generic
485 register "hid" = ""ELAN0001""
486 register "desc" = ""ELAN Touchscreen""
487 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
488 register "detect" = "1"
489 register "reset_gpio" =
490 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
491 register "reset_delay_ms" = "20"
492 register "enable_gpio" =
493 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
494 register "enable_delay_ms" = "1"
495 register "has_power_resource" = "true"
496 device i2c 10 on end
497 end
498 end
499 device ref i2c5 on
500 chip drivers/i2c/generic
501 register "hid" = ""ELAN0000""
502 register "desc" = ""ELAN Touchpad""
503 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
504 register "wake" = "GPE0_DW2_14"
505 register "detect" = "1"
506 device i2c 15 on end
507 end
508 chip drivers/i2c/hid
509 register "generic.hid" = ""SYNA0000""
510 register "generic.cid" = ""ACPI0C50""
511 register "generic.desc" = ""Synaptics Touchpad""
512 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
513 register "generic.wake" = "GPE0_DW2_14"
514 register "generic.detect" = "1"
515 register "hid_desc_reg_offset" = "0x20"
516 device i2c 2c on end
517 end
518 end
519 device ref hda on
520 chip drivers/generic/max98357a
521 register "hid" = ""MX98357A""
522 register "sdmode_gpio" =
523 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
524 register "sdmode_delay" = "5"
525 device generic 0 on
526 probe AUDIO AUDIO_MAX98357_ALC5682I_I2S
527 probe AUDIO AUDIO_MAX98357_ALC5682I_VS_I2S
528 end
529 end
530 chip drivers/sof
531 register "spkr_tplg" = "max98357a"
532 register "jack_tplg" = "rt5682"
533 register "mic_tplg" = "_2ch_pdm0"
534 device generic 0 on end
535 end
536 end
537 device ref pcie_rp5 on
538 chip soc/intel/common/block/pcie/rtd3
539 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
540 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
541 register "srcclk_pin" = "2"
542 device generic 0 on end
543 end
544 register "pch_pcie_rp[PCH_RP(5)]" = "{
545 .clk_src = 2,
546 .clk_req = 2,
547 .flags = PCIE_RP_LTR | PCIE_RP_AER,
548 }"
549 end
550 device ref pcie_rp6 off end
551 device ref pcie_rp8 on
552 chip soc/intel/common/block/pcie/rtd3
553 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
554 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
555 register "srcclk_pin" = "3"
556 device generic 0 on
557 probe DB_SD DB_SD_OZ711LV2LN
558 end
559 end
560 end
561 device ref pcie_rp9 on
562 # Enable PCIE 9 using clk 0 for eMMC
563 register "pch_pcie_rp[PCH_RP(9)]" = "{
564 .clk_src = 0,
565 .clk_req = 0,
566 .flags = PCIE_RP_LTR | PCIE_RP_AER,
567 .pcie_rp_aspm = ASPM_L1,
568 }"
569 probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
570 end
571 device ref gspi1 on
572 chip drivers/spi/acpi
573 register "name" = ""CRFP""
574 register "hid" = "ACPI_DT_NAMESPACE_HID"
575 register "uid" = "1"
576 register "compat_string" = ""google,cros-ec-spi""
577 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
578 register "wake" = "GPE0_DW2_15"
579 register "has_power_resource" = "true"
580 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
581 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
582 register "enable_delay_ms" = "3"
583 device spi 0 hidden end
584 end # FPMCU
585 end
586 device ref pch_espi on
587 chip ec/google/chromeec
588 use conn0 as mux_conn[0]
589 use conn1 as mux_conn[1]
590 device pnp 0c09.0 on end
591 end
592 end
593 device ref pmc hidden
594 chip drivers/intel/pmc_mux
595 device generic 0 on
596 chip drivers/intel/pmc_mux/conn
597 use usb2_port1 as usb2_port
598 use tcss_usb3_port1 as usb3_port
599 device generic 0 alias conn0 on end
600 end
601 chip drivers/intel/pmc_mux/conn
602 use usb2_port3 as usb2_port
603 use tcss_usb3_port3 as usb3_port
604 device generic 2 alias conn1 on end
605 end
606 end
607 end
608 end
609 device ref tcss_xhci on
610 chip drivers/usb/acpi
611 device ref tcss_root_hub on
612 chip drivers/usb/acpi
613 register "desc" = ""USB3 Type-C Port C0 (MLB)""
614 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
615 register "use_custom_pld" = "true"
616 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
617 device ref tcss_usb3_port1 on end
618 end
619 chip drivers/usb/acpi
620 register "desc" = ""USB3 Type-C Port C1 (DB)""
621 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
622 register "use_custom_pld" = "true"
623 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
624 register "usb_lpm_incapable" = "true"
625 device ref tcss_usb3_port3 on
626 probe DB_USB DB_USB3_NO_A
627 probe DB_USB DB_USB3_1C_1A
628 end
629 end
630 end
631 end
632 end
633 device ref xhci on
634 chip drivers/usb/acpi
635 device ref xhci_root_hub on
636 chip drivers/usb/acpi
637 register "desc" = ""USB2 Type-C Port C0 (MLB)""
638 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
639 register "use_custom_pld" = "true"
640 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
641 device ref usb2_port1 on end
642 end
643 chip drivers/usb/acpi
644 register "desc" = ""USB2 Type-C Port C1 (DB)""
645 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
646 register "use_custom_pld" = "true"
647 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
648 device ref usb2_port3 on
649 probe DB_USB DB_USB3_NO_A
650 probe DB_USB DB_USB3_1C_1A
651 end
652 end
653 chip drivers/usb/acpi
654 register "desc" = ""USB2 Camera""
655 register "type" = "UPC_TYPE_INTERNAL"
656 device ref usb2_port6 on
657 end
658 end
659 chip drivers/usb/acpi
660 register "desc" = ""USB2 Type-A Port (DB)""
661 register "type" = "UPC_TYPE_A"
662 register "use_custom_pld" = "true"
663 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
664 register "group" = "ACPI_PLD_GROUP(3, 1)"
665 device ref usb2_port7 on
666 probe DB_USB DB_USB3_1C_1A
667 end
668 end
669 chip drivers/usb/acpi
670 register "desc" = ""USB2 Type-A Port (MLB)""
671 register "type" = "UPC_TYPE_A"
672 register "use_custom_pld" = "true"
673 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))"
674 device ref usb2_port9 on end
675 end
676 chip drivers/usb/acpi
677 register "desc" = ""USB2 Bluetooth""
678 register "type" = "UPC_TYPE_INTERNAL"
679 register "reset_gpio" =
680 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
681 device ref usb2_port10 on end
682 end
683 chip drivers/usb/acpi
684 register "desc" = ""USB3 Type-A Port (MLB)""
685 register "type" = "UPC_TYPE_USB3_A"
686 register "use_custom_pld" = "true"
687 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))"
688 device ref usb3_port1 on end
689 end
690 chip drivers/usb/acpi
691 register "desc" = ""USB3 Type-A Port (DB)""
692 register "type" = "UPC_TYPE_USB3_A"
693 register "use_custom_pld" = "true"
694 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
695 device ref usb3_port3 on
696 probe DB_USB DB_USB3_1C_1A
697 end
698 end
699 end
700 end
701 end
702 end
703 end
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