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mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support
[coreboot.git] / src / mainboard / google / brya / variants / teliks / overridetree.cb
blob8bff4b6fcf406742710c78d8080e260f8927a612
1 fw_config
2 field WIFI 8 9
3 option UNKNOWN 0
4 option WIFI_6_7921 1
5 option WIFI_6E 2
6 option WIFI_6_8852 3
7 end
8 field CAMERA 10 11
9 option UF_720P_WF 0
10 option UF_1080P 1
11 option UF_720P 2
12 option UF_1080P_WF 3
13 end
14 end
15
16 chip soc/intel/alderlake
17 register "sagv" = "SaGv_Enabled"
18
19 # EMMC Tx CMD Delay
20 # Refer to EDS-Vol2-42.3.7.
21 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
22 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
23 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
24
25 # EMMC TX DATA Delay 1
26 # Refer to EDS-Vol2-42.3.8.
27 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
28 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
29 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
30
31 # EMMC TX DATA Delay 2
32 # Refer to EDS-Vol2-42.3.9.
33 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
34 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
35 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
36 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
37 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
38
39 # EMMC RX CMD/DATA Delay 1
40 # Refer to EDS-Vol2-42.3.10.
41 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
42 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
43 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
44 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
45 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
46
47 # EMMC RX CMD/DATA Delay 2
48 # Refer to EDS-Vol2-42.3.12.
49 # [17:16] stands for Rx Clock before Output Buffer,
50 # 00: Rx clock after output buffer,
51 # 01: Rx clock before output buffer,
52 # 10: Automatic selection based on working mode.
53 # 11: Reserved
54 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
55 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
56 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004C"
57
58 # EMMC Rx Strobe Delay
59 # Refer to EDS-Vol2-42.3.11.
60 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
61 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
62 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
63
64 # SOC Aux orientation override:
65 # This is a bitfield that corresponds to up to 4 TCSS ports.
66 # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
67 # TcssAuxOri = 0100b
68 # Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
69 # Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
70 # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
71 # motherboard to USBC connector
72 register "tcss_aux_ori" = "5"
73
74 register "typec_aux_bias_pads[0]" = "{
75 .pad_auxp_dc = GPP_A19,
76 .pad_auxn_dc = GPP_A20
77 }"
78
79 register "typec_aux_bias_pads[1]" = "{
80 .pad_auxp_dc = GPP_E22,
81 .pad_auxn_dc = GPP_E23
82 }"
83
84 # FIVR configurations for teliks are disabled since the board doesn't have V1p05 and Vnn
85 # bypass rails implemented.
86 register "ext_fivr_settings" = "{
87 .configure_ext_fivr = 0,
88 }"
89
90 # Enable the Cnvi BT Audio Offload
91 register "cnvi_bt_audio_offload" = "1"
92
93 # Intel Common SoC Config
94 #+-------------+------------------------------+
95 #| Field | Value |
96 #+-------------+------------------------------+
97 #| I2C0 | TPM. Early init is |
98 #| | required to set up a BAR |
99 #| | for TPM communication |
100 #| I2C1 | Touchscreen |
101 #| I2C2 | Sub-board(PSensor)/WCAM |
102 #| I2C3 | Audio |
103 #| I2C5 | Trackpad |
104 #+-------------+------------------------------+
105 register "common_soc_config" = "{
106 .i2c[0] = {
107 .early_init = 1,
108 .speed = I2C_SPEED_FAST_PLUS,
109 .speed_config[0] = {
110 .speed = I2C_SPEED_FAST_PLUS,
111 .scl_lcnt = 55,
112 .scl_hcnt = 30,
113 .sda_hold = 7,
114 }
115 },
116 .i2c[1] = {
117 .speed = I2C_SPEED_FAST,
118 .speed_config[0] = {
119 .speed = I2C_SPEED_FAST,
120 .scl_lcnt = 160,
121 .scl_hcnt = 79,
122 .sda_hold = 7,
123 }
124 },
125 .i2c[2] = {
126 .speed = I2C_SPEED_FAST,
127 .speed_config[0] = {
128 .speed = I2C_SPEED_FAST,
129 .scl_lcnt = 157,
130 .scl_hcnt = 79,
131 .sda_hold = 7,
132 }
133 },
134 .i2c[3] = {
135 .speed = I2C_SPEED_FAST,
136 .speed_config[0] = {
137 .speed = I2C_SPEED_FAST,
138 .scl_lcnt = 157,
139 .scl_hcnt = 79,
140 .sda_hold = 7,
141 }
142 },
143 .i2c[5] = {
144 .speed = I2C_SPEED_FAST,
145 .speed_config[0] = {
146 .speed = I2C_SPEED_FAST,
147 .scl_lcnt = 152,
148 .scl_hcnt = 79,
149 .sda_hold = 7,
150 }
151 },
152 }"
153
154 # Power limit config
155 register "power_limits_config[ADL_N_041_6W_CORE]" = "{
156 .tdp_pl1_override = 15,
157 .tdp_pl2_override = 25,
158 .tdp_pl4 = 78,
159 }"
160
161 device domain 0 on
162 device ref dtt on
163 chip drivers/intel/dptf
164 ## sensor information
165 register "options.tsr[0].desc" = ""CPU_VR""
166 register "options.tsr[1].desc" = ""CPU""
167 register "options.tsr[2].desc" = ""Ambient""
168 register "options.tsr[3].desc" = ""Charger""
169
170 # TODO: below values are initial reference values only
171 ## Passive Policy
172 register "policies.passive" = "{
173 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
174 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
175 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
176 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
177 [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 75, 5000),
178 }"
179
180 ## Critical Policy
181 register "policies.critical" = "{
182 [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
183 [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN),
184 }"
185
186 register "controls.power_limits" = "{
187 .pl1 = {
188 .min_power = 6000,
189 .max_power = 15000,
190 .time_window_min = 28 * MSECS_PER_SEC,
191 .time_window_max = 32 * MSECS_PER_SEC,
192 .granularity = 200
193 },
194 .pl2 = {
195 .min_power = 25000,
196 .max_power = 25000,
197 .time_window_min = 28 * MSECS_PER_SEC,
198 .time_window_max = 32 * MSECS_PER_SEC,
199 .granularity = 1000
200 }
201 }"
202
203 ## Charger Performance Control (Control, mA)
204 register "controls.charger_perf" = "{
205 [0] = { 255, 3000 },
206 [1] = { 24, 1500 },
207 [2] = { 16, 1000 },
208 [3] = { 8, 500 }
209 }"
210
211 device generic 0 on end
212 end
213 end
214 device ref igpu on
215 chip drivers/gfx/generic
216 register "device_count" = "4"
217 # DDIA for eDP
218 register "device[0].name" = ""LCD0""
219 # Internal panel on the first port of the graphics chip
220 register "device[0].type" = "panel"
221 # DDIB for HDMI
222 # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
223 register "device[1].name" = ""DD01""
224 # TCP0 (DP-1) for port C0
225 register "device[2].name" = ""DD02""
226 register "device[2].use_pld" = "true"
227 register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
228 # TCP1 (DP-2) for port C1
229 register "device[3].name" = ""DD03""
230 register "device[3].use_pld" = "true"
231 register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
232 device generic 0 on end
233 end
234 end
235 device ref ipu on
236 chip drivers/intel/mipi_camera
237 register "acpi_uid" = "0x50000"
238 register "acpi_name" = ""IPU0""
239 register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
240
241 register "cio2_num_ports" = "1"
242 register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
243 register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
244 register "cio2_prt[0]" = "1"
245 device generic 0 on
246 probe CAMERA UF_720P_WF
247 probe CAMERA UF_1080P_WF
248 end
249 end
250 end
251 device ref i2c1 on
252 chip drivers/i2c/hid
253 register "generic.hid" = ""ILTK0001""
254 register "generic.desc" = ""ILITEK Touchscreen""
255 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
256 register "generic.detect" = "1"
257 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
258 register "generic.reset_delay_ms" = "200"
259 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
260 register "generic.enable_delay_ms" = "12"
261 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
262 register "generic.stop_off_delay_ms" = "200"
263 register "generic.has_power_resource" = "1"
264 register "hid_desc_reg_offset" = "0x01"
265 device i2c 41 on end
266 end
267 chip drivers/generic/gpio_keys
268 register "name" = ""PENH""
269 register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
270 register "key.wake_gpe" = "GPE0_DW2_15"
271 register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
272 register "key.wakeup_event_action" = "EV_ACT_ANY"
273 register "key.dev_name" = ""EJCT""
274 register "key.linux_code" = "SW_PEN_INSERTED"
275 register "key.linux_input_type" = "EV_SW"
276 register "key.label" = ""pen_eject""
277 device generic 0 on end
278 end
279 end
280 device ref i2c2 on
281 chip drivers/intel/mipi_camera
282 register "acpi_hid" = ""OVTIDB10""
283 register "acpi_uid" = "0"
284 register "acpi_name" = ""CAM0""
285 register "chip_name" = ""Ov 13b10 Camera""
286 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
287
288 register "ssdb.lanes_used" = "4"
289 register "ssdb.vcm_type" = "0x0C"
290 register "vcm_name" = ""VCM0""
291 register "num_freq_entries" = "1"
292 register "link_freq[0]" = "560 * MHz"
293 register "remote_name" = ""IPU0""
294
295 register "has_power_resource" = "true"
296 #Controls
297 register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
298 register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
299
300 register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X
301 register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1200_WCAM_X
302 register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L
303
304 #_ON
305 register "on_seq.ops_cnt" = "5"
306 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
307 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
308 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
309 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
310 register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
311
312 #_OFF
313 register "off_seq.ops_cnt" = "4"
314 register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
315 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
316 register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
317 register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
318
319 device i2c 36 on
320 probe CAMERA UF_720P_WF
321 probe CAMERA UF_1080P_WF
322 end
323 end
324 chip drivers/intel/mipi_camera
325 register "acpi_uid" = "2"
326 register "acpi_name" = ""VCM0""
327 register "chip_name" = ""DW9714 VCM ""
328 register "device_type" = "INTEL_ACPI_CAMERA_VCM"
329
330 register "vcm_compat" = ""dongwoon,dw9714""
331
332 register "has_power_resource" = "true"
333 #Controls
334 register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_AFVDD
335
336 #_ON
337 register "on_seq.ops_cnt" = "1"
338 register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
339
340 #_OFF
341 register "off_seq.ops_cnt" = "1"
342 register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
343
344 device i2c 0C on
345 probe CAMERA UF_720P_WF
346 probe CAMERA UF_1080P_WF
347 end
348 end
349 chip drivers/intel/mipi_camera
350 register "acpi_uid" = "1"
351 register "acpi_name" = ""NVM0""
352 register "chip_name" = ""GT24P64E""
353 register "device_type" = "INTEL_ACPI_CAMERA_NVM"
354
355 register "nvm_size" = "0x2000"
356 register "nvm_pagesize" = "1"
357 register "nvm_readonly" = "1"
358 register "nvm_width" = "0x10"
359 register "nvm_compat" = ""atmel,24c64""
360
361 device i2c 50 on
362 probe CAMERA UF_720P_WF
363 probe CAMERA UF_1080P_WF
364 end
365 end
366 end
367 device ref i2c3 on
368 chip drivers/i2c/rt5645
369 register "hid" = ""10EC5650""
370 register "name" = ""RT58""
371 register "desc" = ""Realtek RT5650""
372 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
373 register "cbj_sleeve" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
374 register "jd_mode" = "2"
375 device i2c 1a on end
376 end
377 end
378 device ref i2c5 on
379 chip drivers/i2c/hid
380 register "generic.hid" = ""PNP0C50""
381 register "generic.desc" = ""PRIMAX Touchpad""
382 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
383 register "generic.wake" = "GPE0_DW2_14"
384 register "generic.detect" = "1"
385 register "hid_desc_reg_offset" = "0x01"
386 device i2c 15 on end
387 end
388 end
389 device ref cnvi_wifi on
390 chip drivers/wifi/generic
391 register "wake" = "GPE0_PME_B0"
392 register "enable_cnvi_ddr_rfim" = "true"
393 register "add_acpi_dma_property" = "true"
394 device generic 0 on
395 probe WIFI WIFI_6E
396 end
397 end
398 end
399 device ref pcie_rp4 on
400 # PCIe 4 WLAN
401 register "pch_pcie_rp[PCH_RP(4)]" = "{
402 .clk_src = 2,
403 .clk_req = 2,
404 .flags = PCIE_RP_LTR | PCIE_RP_AER,
405 }"
406 chip drivers/wifi/generic
407 register "wake" = "GPE0_DW1_03"
408 register "add_acpi_dma_property" = "true"
409 device pci 00.0 on
410 probe WIFI WIFI_6_7921
411 probe WIFI WIFI_6_8852
412 end
413 end
414 end
415 device ref pch_espi on
416 chip ec/google/chromeec
417 use conn0 as mux_conn[0]
418 use conn1 as mux_conn[1]
419 device pnp 0c09.0 on end
420 end
421 end
422 device ref pmc hidden
423 chip drivers/intel/pmc_mux
424 device generic 0 on
425 chip drivers/intel/pmc_mux/conn
426 use usb2_port1 as usb2_port
427 use tcss_usb3_port2 as usb3_port
428 device generic 0 alias conn0 on end
429 end
430 chip drivers/intel/pmc_mux/conn
431 use usb2_port2 as usb2_port
432 use tcss_usb3_port1 as usb3_port
433 device generic 1 alias conn1 on end
434 end
435 end
436 end
437 end
438 device ref tcss_xhci on
439 chip drivers/usb/acpi
440 device ref tcss_root_hub on
441 chip drivers/usb/acpi
442 register "desc" = ""USB3 Type-C Port C0 (MLB)""
443 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
444 register "use_custom_pld" = "true"
445 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
446 device ref tcss_usb3_port2 on end
447 end
448 chip drivers/usb/acpi
449 register "desc" = ""USB3 Type-C Port C1 (DB)""
450 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
451 register "use_custom_pld" = "true"
452 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
453 device ref tcss_usb3_port1 on end
454 end
455 end
456 end
457 end
458 device ref xhci on
459 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch)
460 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch)
461 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch)
462 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch)
463 register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch)
464 register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
465 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
466 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
467
468 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB))
469 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB)
470 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE)
471 chip drivers/usb/acpi
472 device ref xhci_root_hub on
473 chip drivers/usb/acpi
474 register "desc" = ""USB2 Type-C Port C0 (MLB)""
475 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
476 register "use_custom_pld" = "true"
477 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
478 device ref usb2_port1 on end
479 end
480 chip drivers/usb/acpi
481 register "desc" = ""USB2 Type-C Port C1 (DB)""
482 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
483 register "use_custom_pld" = "true"
484 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
485 device ref usb2_port2 on end
486 end
487 chip drivers/usb/acpi
488 register "desc" = ""USB2 Type-A Port A0 (MLB)""
489 register "type" = "UPC_TYPE_A"
490 register "use_custom_pld" = "true"
491 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
492 device ref usb2_port3 on end
493 end
494 chip drivers/usb/acpi
495 register "desc" = ""USB2 Type-A Port A1 (DB)""
496 register "type" = "UPC_TYPE_A"
497 register "use_custom_pld" = "true"
498 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
499 device ref usb2_port4 on end
500 end
501 chip drivers/usb/acpi
502 register "desc" = ""USB2 LTE""
503 register "type" = "UPC_TYPE_INTERNAL"
504 device ref usb2_port5 on end
505 end
506 chip drivers/usb/acpi
507 register "desc" = ""USB2 UFC""
508 register "type" = "UPC_TYPE_INTERNAL"
509 device ref usb2_port6 on end
510 end
511 chip drivers/usb/acpi
512 register "desc" = ""PCIe Bluetooth""
513 register "type" = "UPC_TYPE_INTERNAL"
514 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
515 device ref usb2_port8 on
516 probe WIFI WIFI_6_7921
517 probe WIFI WIFI_6_8852
518 end
519 end
520 chip drivers/usb/acpi
521 register "desc" = ""CNVi Bluetooth""
522 register "type" = "UPC_TYPE_INTERNAL"
523 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
524 device ref usb2_port10 on
525 probe WIFI WIFI_6E
526 end
527 end
528 chip drivers/usb/acpi
529 register "desc" = ""USB3 Type-A Port A0 (MLB)""
530 register "type" = "UPC_TYPE_USB3_A"
531 register "use_custom_pld" = "true"
532 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
533 device ref usb3_port1 on end
534 end
535 chip drivers/usb/acpi
536 register "desc" = ""USB3 Type-A Port A1 (DB)""
537 register "type" = "UPC_TYPE_USB3_A"
538 register "use_custom_pld" = "true"
539 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
540 device ref usb3_port2 on end
541 end
542 chip drivers/usb/acpi
543 register "desc" = ""USB3 WWAN""
544 register "type" = "UPC_TYPE_INTERNAL"
545 device ref usb3_port3 on end
546 end
547 chip drivers/usb/acpi
548 register "desc" = ""USB3 WLAN""
549 register "type" = "UPC_TYPE_INTERNAL"
550 device ref usb3_port4 on end
551 end
552 end
553 end
554 end
555 device ref pcie_rp7 off end # SDCard
556 device ref hda on
557 chip drivers/sof
558 register "spkr_tplg" = "rt5650_sp"
559 register "jack_tplg" = "rt5650_hp"
560 register "mic_tplg" = "_2ch_pdm0"
561 device generic 0 on end
562 end
563 end
564 end
565 end
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