src/mainboard/google/brya/variants/telith/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A11 : GPP_A11 ==> EN_SPK_PA */
  11         PAD_CFG_GPO(GPP_A11, 0, DEEP),
  12         /* A18 : NC ==> HDMI_HPD_SRC*/
  13         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  14
  15         /* A20 : DDSP_HPD2 ==> NC */
  16         PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
  17         /* A21 : GPP_A21 ==> NC */
  18         PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG),
  19         /* A22 : GPP_A22 ==> NC */
  20         PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
  21
  22         /* B5  : I2C2_SDA ==> MIPI_WCAM_SDA */
  23         PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
  24         /* B6  : I2C2_SCL ==> MIPI_WCAM_SCL */
  25         PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
  26
  27         /* B11 : NC ==> EN_PP3300_WLAN_X*/
  28         PAD_CFG_GPO(GPP_B11, 0, DEEP),
  29
  30         /* D8  : SRCCLKREQ3# ==> NC */
  31         PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
  32         /* D13 : NC ==> EN_PP1800_WCAM_X */
  33         PAD_CFG_GPO_LOCK(GPP_D13, 1, LOCK_CONFIG),
  34
  35         /* E20 : DDP2_CTRLCLK ==> NC */
  36         PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
  37         /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
  38         PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
  39
  40         /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
  41         PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
  42
  43         /* F6  : CNV_PA_BLANKING ==> NC */
  44         PAD_NC(GPP_F6, NONE),
  45         /* F15 : GSXSRESET# ==> GPIO */
  46         PAD_CFG_GPO(GPP_F15, 0, DEEP),
  47         /* F13 : GSXSLOAD ==> GPIO */
  48         PAD_CFG_GPO(GPP_F13, 0, DEEP),
  49         /* F18 : THC1_SPI2_INT# ==> NC */
  50         PAD_NC(GPP_F18, NONE),
  51         /* F23 : V1P05_CTRL ==> NC*/
  52         PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG),
  53
  54         /* H8  : CNV_MFUART2_RXD ==> NC */
  55         PAD_NC(GPP_H8, NONE),
  56         /* H9  : CNV_MFUART2_TXD ==> NC */
  57         PAD_NC(GPP_H9, NONE),
  58         /* H12 : UART0_RTS# ==> NC*/
  59         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
  60         /* H13 : UART0_CTS# ==> NC */
  61         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
  62         /* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
  63         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
  64         /* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */
  65         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
  66
  67         /* R6 : DMIC_CLK_A_1A ==> NC */
  68         PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
  69         /* R7 : DMIC_DATA_1A ==> NC */
  70         PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
  71
  72         /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
  73         /* BT_I2S_BCLK */
  74         PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
  75         /* BT_I2S_SYNC */
  76         PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
  77         /* BT_I2S_SDO */
  78         PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
  79         /* BT_I2S_SDI */
  80         PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
  81         /* SSP2_SCLK */
  82         PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
  83         /* SSP2_SFRM */
  84         PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
  85         /* SSP_TXD */
  86         PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
  87         /* SSP_RXD */
  88         PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
  89 };
  90
  91 /* Early pad configuration in bootblock */
  92 static const struct pad_config early_gpio_table[] = {
  93         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
  94         PAD_CFG_GPO(GPP_C0, 1, DEEP),
  95         /* C1  : SMBDATA ==> TCHSCR_RST_L */
  96         PAD_CFG_GPO(GPP_C1, 1, DEEP),
  97
  98         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
  99         PAD_CFG_GPO(GPP_H20, 0, DEEP),
 100         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 101         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 102         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 103         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 104
 105
 106         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 107         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 108         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 109         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 110
 111         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
 112         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 113         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 114         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 115 };
 116
 117 const struct pad_config *variant_gpio_override_table(size_t *num)
 118 {
 119         *num = ARRAY_SIZE(override_gpio_table);
 120         return override_gpio_table;
 121 }
 122
 123 const struct pad_config *variant_early_gpio_table(size_t *num)
 124 {
 125         *num = ARRAY_SIZE(early_gpio_table);
 126         return early_gpio_table;
 127 }