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mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support
[coreboot.git] / src / mainboard / google / brya / variants / trulo / overridetree.cb
blobd135db0bd1af9a9906467fc5a6da61e0d511cdc5
1 fw_config
2 field THERMAL_SOLUTION 0 0
3 option THERMAL_SOLUTION_6W 0
4 option THERMAL_SOLUTION_15W 1
5 end
6 field PDC_CONTROL 1 2
7 option PDC_CONTROL_UNKNOWN 0
8 option PDC_RTS_BYPASS 1
9 option PDC_TI_BYPASS 2
10 end
11 field STORAGE 30 31
12 option STORAGE_EMMC 0
13 option STORAGE_NVME 1
14 option STORAGE_UFS 2
15 option STORAGE_UNKNOWN 3
16 end
17 end
18
19 chip soc/intel/alderlake
20 register "sagv" = "SaGv_Enabled"
21
22 # S0ix enable
23 register "s0ix_enable" = "true"
24
25 # DPTF enable
26 register "dptf_enable" = "1"
27
28 register "tcc_offset" = "10" # TCC of 90
29
30 # Enable CNVi BT
31 register "cnvi_bt_core" = "true"
32
33 # eMMC HS400
34 register "emmc_enable_hs400_mode" = "true"
35
36 #eMMC DLL tuning parameters
37 # EMMC Tx CMD Delay
38 # Refer to EDS-Vol2-42.3.7.
39 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
40 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
41 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
42
43 # EMMC TX DATA Delay 1
44 # Refer to EDS-Vol2-42.3.8.
45 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
46 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
47 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
48
49 # EMMC TX DATA Delay 2
50 # Refer to EDS-Vol2-42.3.9.
51 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
52 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
53 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
54 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
55 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
56
57 # EMMC RX CMD/DATA Delay 1
58 # Refer to EDS-Vol2-42.3.10.
59 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
60 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
61 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
62 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
63 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
64
65 # EMMC RX CMD/DATA Delay 2
66 # Refer to EDS-Vol2-42.3.12.
67 # [17:16] stands for Rx Clock before Output Buffer,
68 # 00: Rx clock after output buffer,
69 # 01: Rx clock before output buffer,
70 # 10: Automatic selection based on working mode.
71 # 11: Reserved
72 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
73 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
74 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E"
75
76 # EMMC Rx Strobe Delay
77 # Refer to EDS-Vol2-42.3.11.
78 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
79 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
80 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
81
82 register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # USB2_A0(MLB)
83 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 (DB)
84 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
85 register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 (MLB)
86
87 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 (MLB)
88 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 (DB)
89
90 register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
91
92 # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
93 # Bit 2 - C1 has a redriver which does SBU muxing.
94 # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
95 register "tcss_aux_ori" = "0"
96
97 # HD Audio
98 register "pch_hda_dsp_enable" = "1"
99 register "pch_hda_audio_link_hda_enable" = "1"
100 register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
101 register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
102 register "pch_hda_idisp_codec_enable" = "1"
103
104 # Configure external V1P05/Vnn/VnnSx Rails
105 register "ext_fivr_settings" = "{
106 .configure_ext_fivr = 1,
107 .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
108 .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
109 .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
110 .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
111 .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
112 .v1p05_voltage_mv = 1050,
113 .vnn_voltage_mv = 780,
114 .vnn_sx_voltage_mv = 1050,
115 .v1p05_icc_max_ma = 500,
116 .vnn_icc_max_ma = 500,
117 }"
118
119 register "serial_io_i2c_mode" = "{
120 [PchSerialIoIndexI2C0] = PchSerialIoPci,
121 [PchSerialIoIndexI2C1] = PchSerialIoPci,
122 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
123 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
124 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
125 [PchSerialIoIndexI2C5] = PchSerialIoPci,
126 }"
127
128 register "serial_io_gspi_mode" = "{
129 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
130 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
131 }"
132
133 register "serial_io_uart_mode" = "{
134 [PchSerialIoIndexUART0] = PchSerialIoPci,
135 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
136 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
137 }"
138
139 # FIXME: To be enabled in future based on PNP impact data.
140 # Disable Package C-state demotion for nissa baseboard.
141 register "disable_package_c_state_demotion" = "true"
142
143 # Intel Common SoC Config
144 #+-------------------+---------------------------+
145 #| Field | Value |
146 #+-------------------+---------------------------+
147 #| I2C0 | TPM. Early init is |
148 #| | required to set up a BAR |
149 #| | for TPM communication |
150 #| I2C1 | Trackpad |
151 #| I2C5 | Touchscreen |
152 #+-------------------+---------------------------+
153 register "common_soc_config" = "{
154 .i2c[0] = {
155 .early_init = 1,
156 .speed = I2C_SPEED_FAST_PLUS,
157 .speed_config[0] = {
158 .speed = I2C_SPEED_FAST_PLUS,
159 .scl_lcnt = 55,
160 .scl_hcnt = 30,
161 .sda_hold = 7,
162 }
163 },
164 .i2c[1] = {
165 .speed = I2C_SPEED_FAST,
166 .speed_config[0] = {
167 .speed = I2C_SPEED_FAST,
168 .scl_lcnt = 158,
169 .scl_hcnt = 79,
170 .sda_hold = 7,
171 }
172 },
173 .i2c[5] = {
174 .speed = I2C_SPEED_FAST,
175 .speed_config[0] = {
176 .speed = I2C_SPEED_FAST,
177 .scl_lcnt = 158,
178 .scl_hcnt = 79,
179 .sda_hold = 7,
180 }
181 },
182 }"
183
184 device domain 0 on
185 device ref igpu on end
186 device ref dtt on
187 chip drivers/intel/dptf
188 ## sensor information
189 register "options.tsr[0].desc" = ""DDR""
190 register "options.tsr[1].desc" = ""charger""
191 register "options.tsr[2].desc" = ""ambient""
192
193 ## Active Policy
194 register "policies.active" = "{
195 [0] = {
196 .target = DPTF_CPU,
197 .thresholds = {
198 TEMP_PCT(70, 100),
199 TEMP_PCT(60, 65),
200 TEMP_PCT(42, 60),
201 TEMP_PCT(39, 55),
202 TEMP_PCT(38, 50),
203 TEMP_PCT(35, 43),
204 TEMP_PCT(31, 30),
205 }
206 },
207 [1] = {
208 .target = DPTF_TEMP_SENSOR_0,
209 .thresholds = {
210 TEMP_PCT(60, 100),
211 TEMP_PCT(55, 65),
212 TEMP_PCT(52, 60),
213 TEMP_PCT(50, 55),
214 TEMP_PCT(48, 50),
215 TEMP_PCT(45, 43),
216 TEMP_PCT(41, 30),
217 }
218 }
219 }"
220
221 ## Passive Policy
222 register "policies.passive" = "{
223 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
224 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
225 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 70, 5000),
226 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
227 }"
228
229 ## Critical Policy
230 register "policies.critical" = "{
231 [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
232 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
233 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
234 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
235 }"
236
237 register "controls.power_limits" = "{
238 .pl1 = {
239 .min_power = 5000,
240 .max_power = 6000,
241 .time_window_min = 28 * MSECS_PER_SEC,
242 .time_window_max = 28 * MSECS_PER_SEC,
243 .granularity = 500
244 },
245 .pl2 = {
246 .min_power = 25000,
247 .max_power = 25000,
248 .time_window_min = 32 * MSECS_PER_SEC,
249 .time_window_max = 32 * MSECS_PER_SEC,
250 .granularity = 500
251 }
252 }"
253
254 ## Charger Performance Control (Control, mA)
255 register "controls.charger_perf" = "{
256 [0] = { 255, 1700 },
257 [1] = { 24, 1500 },
258 [2] = { 16, 1000 },
259 [3] = { 8, 500 }
260 }"
261
262 ## Fan Performance Control (Percent, Speed, Noise, Power)
263 register "controls.fan_perf" = "{
264 [0] = { 100, 6000, 220, 2200, },
265 [1] = { 92, 5500, 180, 1800, },
266 [2] = { 85, 5000, 145, 1450, },
267 [3] = { 70, 4400, 115, 1150, },
268 [4] = { 56, 3900, 90, 900, },
269 [5] = { 45, 3300, 55, 550, },
270 [6] = { 38, 3000, 30, 300, },
271 [7] = { 33, 2900, 15, 150, },
272 [8] = { 10, 800, 10, 100, },
273 [9] = { 0, 0, 0, 50, }
274 }"
275
276 ## Fan options
277 register "options.fan.fine_grained_control" = "true"
278 register "options.fan.step_size" = "2"
279
280 device generic 0 on
281 probe THERMAL_SOLUTION THERMAL_SOLUTION_6W
282 end
283 end
284 chip drivers/intel/dptf
285 ## sensor information
286 register "options.tsr[0].desc" = ""DDR""
287 register "options.tsr[1].desc" = ""charger""
288 register "options.tsr[2].desc" = ""ambient""
289
290 ## Active Policy
291 register "policies.active" = "{
292 [0] = {
293 .target = DPTF_CPU,
294 .thresholds = {
295 TEMP_PCT(70, 100),
296 TEMP_PCT(60, 65),
297 TEMP_PCT(42, 58),
298 TEMP_PCT(39, 53),
299 TEMP_PCT(38, 47),
300 TEMP_PCT(35, 43),
301 TEMP_PCT(31, 30),
302 }
303 },
304 [1] = {
305 .target = DPTF_TEMP_SENSOR_0,
306 .thresholds = {
307 TEMP_PCT(60, 100),
308 TEMP_PCT(55, 65),
309 TEMP_PCT(52, 58),
310 TEMP_PCT(50, 53),
311 TEMP_PCT(48, 47),
312 TEMP_PCT(45, 43),
313 TEMP_PCT(41, 30),
314 }
315 }
316 }"
317
318 ## Passive Policy
319 register "policies.passive" = "{
320 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
321 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
322 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 70, 5000),
323 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
324 }"
325
326 ## Critical Policy
327 register "policies.critical" = "{
328 [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
329 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
330 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
331 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
332 }"
333
334 register "controls.power_limits" = "{
335 .pl1 = {
336 .min_power = 14000,
337 .max_power = 15000,
338 .time_window_min = 28 * MSECS_PER_SEC,
339 .time_window_max = 28 * MSECS_PER_SEC,
340 .granularity = 500
341 },
342 .pl2 = {
343 .min_power = 35000,
344 .max_power = 35000,
345 .time_window_min = 32 * MSECS_PER_SEC,
346 .time_window_max = 32 * MSECS_PER_SEC,
347 .granularity = 500
348 }
349 }"
350
351 ## Charger Performance Control (Control, mA)
352 register "controls.charger_perf" = "{
353 [0] = { 255, 1700 },
354 [1] = { 24, 1500 },
355 [2] = { 16, 1000 },
356 [3] = { 8, 500 }
357 }"
358
359 ## Fan Performance Control (Percent, Speed, Noise, Power)
360 register "controls.fan_perf" = "{
361 [0] = { 100, 6000, 220, 2200, },
362 [1] = { 92, 5500, 180, 1800, },
363 [2] = { 85, 5000, 145, 1450, },
364 [3] = { 70, 4400, 115, 1150, },
365 [4] = { 56, 3900, 90, 900, },
366 [5] = { 45, 3300, 55, 550, },
367 [6] = { 38, 3000, 30, 300, },
368 [7] = { 33, 2900, 15, 150, },
369 [8] = { 10, 800, 10, 100, },
370 [9] = { 0, 0, 0, 50, }
371 }"
372
373 ## Fan options
374 register "options.fan.fine_grained_control" = "true"
375 register "options.fan.step_size" = "2"
376
377 device generic 1 on
378 probe THERMAL_SOLUTION THERMAL_SOLUTION_15W
379 end
380 end
381 end
382 device ref tcss_xhci on
383 chip drivers/usb/acpi
384 device ref tcss_root_hub on
385 chip drivers/usb/acpi
386 register "desc" = ""USB3 Type-C Port C0 (MLB)""
387 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
388 register "use_custom_pld" = "true"
389 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
390 device ref tcss_usb3_port1 on end
391 end
392 end
393 end
394 end
395 device ref xhci on
396 chip drivers/usb/acpi
397 device ref xhci_root_hub on
398 chip drivers/usb/acpi
399 register "desc" = ""USB2 Type-A Port A0 (MLB)""
400 register "type" = "UPC_TYPE_A"
401 register "use_custom_pld" = "true"
402 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
403 device ref usb2_port1 on end
404 end
405 chip drivers/usb/acpi
406 register "desc" = ""USB2 Type-A Port A1 (DB)""
407 register "type" = "UPC_TYPE_A"
408 register "use_custom_pld" = "true"
409 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
410 device ref usb2_port2 on end
411 end
412 chip drivers/usb/acpi
413 register "desc" = ""USB2 Camera""
414 register "type" = "UPC_TYPE_INTERNAL"
415 device ref usb2_port3 on end
416 end
417 chip drivers/usb/acpi
418 register "desc" = ""USB2 Type-C Port C0 (MLB)""
419 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
420 register "use_custom_pld" = "true"
421 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
422 device ref usb2_port5 on end
423 end
424 chip drivers/usb/acpi
425 register "desc" = ""USB2 Bluetooth""
426 register "type" = "UPC_TYPE_INTERNAL"
427 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
428 device ref usb2_port10 on end
429 end
430 chip drivers/usb/acpi
431 register "desc" = ""USB3 Type-A Port A0 (MLB)""
432 register "type" = "UPC_TYPE_USB3_A"
433 register "use_custom_pld" = "true"
434 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
435 device ref usb3_port1 on end
436 end
437 chip drivers/usb/acpi
438 register "desc" = ""USB3 Type-A Port A1 (DB)""
439 register "type" = "UPC_TYPE_USB3_A"
440 register "use_custom_pld" = "true"
441 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
442 device ref usb3_port2 on end
443 end
444 end
445 end
446 end
447 device ref shared_sram on end
448 device ref cnvi_wifi on
449 chip drivers/wifi/generic
450 register "wake" = "GPE0_PME_B0"
451 register "enable_cnvi_ddr_rfim" = "true"
452 register "add_acpi_dma_property" = "true"
453 device generic 0 on end
454 end
455 end
456 device ref i2c0 on
457 chip drivers/i2c/tpm
458 register "hid" = ""GOOG0005""
459 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A17_IRQ)"
460 device i2c 50 on end
461 end
462 end #I2C0
463 device ref i2c1 on
464 chip drivers/i2c/generic
465 register "hid" = ""ELAN0000""
466 register "desc" = ""ELAN Touchpad""
467 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
468 register "wake" = "GPE0_DW1_03"
469 register "detect" = "1"
470 device i2c 15 on end
471 end
472 end #I2C1
473 device ref i2c5 on
474 chip drivers/i2c/hid
475 register "generic.hid" = ""ELAN9004""
476 register "generic.desc" = ""ELAN Touchscreen""
477 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
478 register "generic.detect" = "1"
479 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
480 register "generic.reset_delay_ms" = "20"
481 register "generic.reset_off_delay_ms" = "2"
482 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
483 register "generic.enable_delay_ms" = "1"
484 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
485 register "generic.stop_delay_ms" = "150"
486 register "generic.stop_off_delay_ms" = "2"
487 register "generic.has_power_resource" = "1"
488 register "hid_desc_reg_offset" = "0x01"
489 device i2c 10 on end
490 end
491 end #I2C5
492 device ref heci1 on end
493 device ref emmc on
494 probe STORAGE STORAGE_UNKNOWN
495 probe STORAGE STORAGE_EMMC
496 end
497 device ref ufs on
498 probe STORAGE STORAGE_UNKNOWN
499 probe STORAGE STORAGE_UFS
500 end
501 device ref uart0 on end
502 device ref pch_espi on
503 chip ec/google/chromeec
504 device pnp 0c09.0 on end
505 end
506 end
507 device ref pmc hidden end
508 device ref hda on
509 chip drivers/sof
510 register "spkr_tplg" = "max98360a"
511 register "jack_tplg" = "rt5682"
512 register "mic_tplg" = "_2ch_pdm0"
513 device generic 0 on end
514 end
515 end
516 end
517 end
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