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ec/dasharo: Add dependancy to EC_DASHARO_EC_FLASH_SIZE
[coreboot.git] / src / mainboard / google / brya / variants / uldrenite / overridetree.cb
blobf7ff7761a90882a9114530f0fc326001a7be2654
1 chip soc/intel/alderlake
2 register "sagv" = "SaGv_Enabled"
3
4 # S0ix enable
5 register "s0ix_enable" = "true"
6
7 # DPTF enable
8 register "dptf_enable" = "1"
9
10 register "tcc_offset" = "5" # TCC of 100
11
12 # Enable CNVi BT
13 register "cnvi_bt_core" = "true"
14
15 # eMMC HS400
16 register "emmc_enable_hs400_mode" = "true"
17
18 #eMMC DLL tuning parameters
19 # EMMC Tx CMD Delay
20 # Refer to EDS-Vol2-42.3.7.
21 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
22 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
23 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
24
25 # EMMC TX DATA Delay 1
26 # Refer to EDS-Vol2-42.3.8.
27 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
28 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
29 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x311b"
30
31 # EMMC TX DATA Delay 2
32 # Refer to EDS-Vol2-42.3.9.
33 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
34 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
35 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
36 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
37 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C282928"
38
39 # EMMC RX CMD/DATA Delay 1
40 # Refer to EDS-Vol2-42.3.10.
41 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
42 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
43 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
44 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
45 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C19593B"
46
47 # EMMC RX CMD/DATA Delay 2
48 # Refer to EDS-Vol2-42.3.12.
49 # [17:16] stands for Rx Clock before Output Buffer,
50 # 00: Rx clock after output buffer,
51 # 01: Rx clock before output buffer,
52 # 10: Automatic selection based on working mode.
53 # 11: Reserved
54 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
55 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
56 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10026"
57
58 # EMMC Rx Strobe Delay
59 # Refer to EDS-Vol2-42.3.11.
60 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
61 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
62 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01313"
63
64 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
65 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
66 register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB2_A0
67 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
68 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera
69 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera
70
71 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
72
73 register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
74 register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
75
76 # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
77 # Bit 2 - C1 has a redriver which does SBU muxing.
78 # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
79 register "tcss_aux_ori" = "0"
80
81 # HD Audio
82 register "pch_hda_dsp_enable" = "1"
83 register "pch_hda_audio_link_hda_enable" = "1"
84 register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
85 register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
86 register "pch_hda_idisp_codec_enable" = "1"
87
88 # Configure external V1P05/Vnn/VnnSx Rails
89 register "ext_fivr_settings" = "{
90 .configure_ext_fivr = 1,
91 .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
92 .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
93 .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
94 .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
95 .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
96 .v1p05_voltage_mv = 1050,
97 .vnn_voltage_mv = 780,
98 .vnn_sx_voltage_mv = 1050,
99 .v1p05_icc_max_ma = 500,
100 .vnn_icc_max_ma = 500,
101 }"
102
103 register "serial_io_i2c_mode" = "{
104 [PchSerialIoIndexI2C0] = PchSerialIoPci,
105 [PchSerialIoIndexI2C1] = PchSerialIoPci,
106 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
107 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
108 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
109 [PchSerialIoIndexI2C5] = PchSerialIoPci,
110 }"
111
112 register "serial_io_gspi_mode" = "{
113 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
114 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
115 }"
116
117 register "serial_io_uart_mode" = "{
118 [PchSerialIoIndexUART0] = PchSerialIoPci,
119 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
120 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
121 }"
122
123 # FIXME: To be enabled in future based on PNP impact data.
124 # Disable Package C-state demotion for nissa baseboard.
125 register "disable_package_c_state_demotion" = "true"
126
127 # Intel Common SoC Config
128 #+-------------------+---------------------------+
129 #| Field | Value |
130 #+-------------------+---------------------------+
131 #| I2C0 | TPM. Early init is |
132 #| | required to set up a BAR |
133 #| | for TPM communication |
134 #| I2C1 | Trackpad |
135 #| I2C5 | Touchscreen |
136 #+-------------------+---------------------------+
137 register "common_soc_config" = "{
138 .i2c[0] = {
139 .early_init = 1,
140 .speed = I2C_SPEED_FAST_PLUS,
141 .speed_config[0] = {
142 .speed = I2C_SPEED_FAST_PLUS,
143 .scl_lcnt = 55,
144 .scl_hcnt = 30,
145 .sda_hold = 7,
146 }
147 },
148 .i2c[1] = {
149 .speed = I2C_SPEED_FAST,
150 .speed_config[0] = {
151 .speed = I2C_SPEED_FAST,
152 .scl_lcnt = 158,
153 .scl_hcnt = 79,
154 .sda_hold = 7,
155 }
156 },
157 .i2c[5] = {
158 .speed = I2C_SPEED_FAST,
159 .speed_config[0] = {
160 .speed = I2C_SPEED_FAST,
161 .scl_lcnt = 158,
162 .scl_hcnt = 79,
163 .sda_hold = 7,
164 }
165 },
166 }"
167
168 register "power_limits_config[ADL_N_041_6W_CORE]" = "{
169 .tdp_pl1_override = 10,
170 .tdp_pl2_override = 25,
171 .tdp_pl4 = 78,
172 }"
173
174 device domain 0 on
175 device ref igpu on end
176 device ref dtt on
177 chip drivers/intel/dptf
178 ## sensor information
179 register "options.tsr[0].desc" = ""DDR""
180 register "options.tsr[1].desc" = ""charger""
181 register "options.tsr[2].desc" = ""ambient""
182
183 ## Passive Policy
184 register "policies.passive" = "{
185 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
186 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000),
187 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 5000),
188 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000),
189 }"
190
191 ## Critical Policy
192 register "policies.critical" = "{
193 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
194 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 98, SHUTDOWN),
195 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 98, SHUTDOWN),
196 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 98, SHUTDOWN),
197 }"
198
199 register "controls.power_limits" = "{
200 .pl1 = {
201 .min_power = 6000,
202 .max_power = 10000,
203 .time_window_min = 28 * MSECS_PER_SEC,
204 .time_window_max = 28 * MSECS_PER_SEC,
205 .granularity = 500
206 },
207 .pl2 = {
208 .min_power = 25000,
209 .max_power = 25000,
210 .time_window_min = 32 * MSECS_PER_SEC,
211 .time_window_max = 32 * MSECS_PER_SEC,
212 .granularity = 500
213 }
214 }"
215
216 ## Charger Performance Control (Control, mA)
217 register "controls.charger_perf" = "{
218 [0] = { 255, 1700 },
219 [1] = { 24, 1500 },
220 [2] = { 16, 1000 },
221 [3] = { 8, 500 }
222 }"
223
224 device generic 0 on end
225 end
226 end # DPTF
227 device ref tcss_xhci on
228 chip drivers/usb/acpi
229 device ref tcss_root_hub on
230 chip drivers/usb/acpi
231 register "desc" = ""USB3 Type-C Port C0 (MLB)""
232 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
233 register "use_custom_pld" = "true"
234 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
235 device ref tcss_usb3_port1 on end
236 end
237 chip drivers/usb/acpi
238 register "desc" = ""USB3 Type-C Port C1 (MLB)""
239 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
240 register "use_custom_pld" = "true"
241 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
242 device ref tcss_usb3_port2 on end
243 end
244 end
245 end
246 end
247 device ref xhci on
248 chip drivers/usb/acpi
249 device ref xhci_root_hub on
250 chip drivers/usb/acpi
251 register "desc" = ""USB2 Type-C Port C0 (MLB)""
252 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
253 register "use_custom_pld" = "true"
254 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
255 device ref usb2_port1 on end
256 end
257 chip drivers/usb/acpi
258 register "desc" = ""USB2 Type-C Port C1 (MLB)""
259 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
260 register "use_custom_pld" = "true"
261 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
262 device ref usb2_port2 on end
263 end
264 chip drivers/usb/acpi
265 register "desc" = ""USB2 Type-A Port A0 (MLB)""
266 register "type" = "UPC_TYPE_A"
267 register "use_custom_pld" = "true"
268 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
269 device ref usb2_port3 on end
270 end
271 chip drivers/usb/acpi
272 register "desc" = ""USB2 WWAN""
273 register "type" = "UPC_TYPE_INTERNAL"
274 device ref usb2_port5 on end
275 end
276 chip drivers/usb/acpi
277 register "desc" = ""USB2 User Facing Camera""
278 register "type" = "UPC_TYPE_INTERNAL"
279 device ref usb2_port6 on end
280 end
281 chip drivers/usb/acpi
282 register "desc" = ""USB2 World Facing Camera""
283 register "type" = "UPC_TYPE_INTERNAL"
284 device ref usb2_port8 on end
285 end
286 chip drivers/usb/acpi
287 register "desc" = ""USB2 Bluetooth""
288 register "type" = "UPC_TYPE_INTERNAL"
289 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
290 device ref usb2_port10 on end
291 end
292 chip drivers/usb/acpi
293 register "desc" = ""USB3 Type-A Port A0 (MLB)""
294 register "type" = "UPC_TYPE_USB3_A"
295 register "use_custom_pld" = "true"
296 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
297 device ref usb3_port1 on end
298 end
299 end
300 end
301 end
302 device ref cnvi_wifi on
303 chip drivers/wifi/generic
304 register "wake" = "GPE0_PME_B0"
305 register "enable_cnvi_ddr_rfim" = "true"
306 register "add_acpi_dma_property" = "true"
307 device generic 0 on end
308 end
309 end
310 device ref i2c0 on
311 chip drivers/i2c/tpm
312 register "hid" = ""GOOG0005""
313 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A17_IRQ)"
314 device i2c 50 on end
315 end
316 end # I2C0
317 device ref i2c1 on
318 chip drivers/i2c/generic
319 register "hid" = ""ELAN0000""
320 register "desc" = ""ELAN Touchpad""
321 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
322 register "wake" = "GPE0_DW1_03"
323 register "detect" = "1"
324 device i2c 15 on end
325 end
326 chip drivers/i2c/hid
327 register "generic.hid" = ""PNP0C50""
328 register "generic.desc" = ""Cirque Touchpad""
329 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
330 register "generic.detect" = "1"
331 register "generic.wake" = "GPE0_DW1_03"
332 register "hid_desc_reg_offset" = "0x20"
333 device i2c 2c on end
334 end
335 end # I2C1
336 device ref i2c5 on
337 chip drivers/i2c/generic
338 register "hid" = ""ELAN0001""
339 register "desc" = ""ELAN Touchscreen""
340 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
341 register "detect" = "1"
342 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
343 register "reset_delay_ms" = "20"
344 register "reset_off_delay_ms" = "2"
345 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
346 register "stop_delay_ms" = "150"
347 register "stop_off_delay_ms" = "2"
348 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
349 register "enable_delay_ms" = "1"
350 register "has_power_resource" = "true"
351 device i2c 10 on end
352 end # EKTH5012
353 chip drivers/i2c/hid
354 register "generic.hid" = ""ELAN900C""
355 register "generic.desc" = ""ELAN Touchscreen""
356 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
357 register "generic.detect" = "1"
358 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
359 register "generic.reset_delay_ms" = "6"
360 register "generic.reset_off_delay_ms" = "1"
361 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
362 register "generic.enable_delay_ms" = "6"
363 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
364 register "generic.stop_delay_ms" = "150"
365 register "generic.has_power_resource" = "1"
366 register "hid_desc_reg_offset" = "0x01"
367 device i2c 16 on end
368 end # EKTH7D18
369 chip drivers/i2c/hid
370 register "generic.hid" = ""GXTP7996""
371 register "generic.desc" = ""Goodix Touchscreen""
372 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
373 register "generic.detect" = "1"
374 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
375 register "generic.reset_delay_ms" = "100"
376 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
377 register "generic.stop_delay_ms" = "200"
378 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
379 register "generic.enable_delay_ms" = "10"
380 register "generic.has_power_resource" = "1"
381 register "hid_desc_reg_offset" = "0x01"
382 device i2c 5d on end
383 end # GXTP7996
384 chip drivers/i2c/hid
385 register "generic.hid" = ""WDHT0002""
386 register "generic.desc" = ""WDT Touchscreen""
387 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
388 register "generic.detect" = "1"
389 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
390 register "generic.reset_delay_ms" = "20"
391 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
392 register "generic.stop_delay_ms" = "130"
393 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
394 register "generic.enable_delay_ms" = "1"
395 register "generic.has_power_resource" = "1"
396 register "hid_desc_reg_offset" = "0x20"
397 device i2c 2c on end
398 end # WDT8752A
399 chip drivers/i2c/hid
400 register "generic.hid" = ""WDHT2601""
401 register "generic.desc" = ""WDT Touchscreen""
402 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
403 register "generic.detect" = "1"
404 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
405 register "generic.reset_delay_ms" = "20"
406 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
407 register "generic.stop_delay_ms" = "130"
408 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
409 register "generic.enable_delay_ms" = "1"
410 register "generic.has_power_resource" = "1"
411 register "hid_desc_reg_offset" = "0x20"
412 device i2c 3c on end
413 end # WDT8790A
414 chip drivers/i2c/hid
415 register "generic.hid" = ""GTCH7502""
416 register "generic.desc" = ""G2TOUCH Touchscreen""
417 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
418 register "generic.detect" = "1"
419 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
420 register "generic.reset_delay_ms" = "100"
421 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
422 register "generic.stop_delay_ms" = "30"
423 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
424 register "generic.enable_delay_ms" = "30"
425 register "generic.has_power_resource" = "1"
426 register "hid_desc_reg_offset" = "0x01"
427 device i2c 40 on end
428 end # GTCH7502
429 end # I2C5
430 device ref pcie_rp2 on
431 # Enable WWAN Card PCIE 2 using clk 2
432 register "pch_pcie_rp[PCH_RP(2)]" = "{
433 .clk_src = 2,
434 .clk_req = 2,
435 .flags = PCIE_RP_LTR | PCIE_RP_AER,
436 }"
437 chip soc/intel/common/block/pcie/rtd3
438 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F13)"
439 register "reset_off_delay_ms" = "20"
440 register "srcclk_pin" = "2"
441 register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
442 register "skip_on_off_support" = "true"
443 device generic 0 alias rp2_rtd3 on end
444 end
445 chip drivers/wwan/fm
446 register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H23)"
447 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F12)"
448 register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F13)"
449 register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
450 register "add_acpi_dma_property" = "true"
451 use rp2_rtd3 as rtd3dev
452 device generic 0 alias rp2_wwan on end
453 end
454 end # PCIE2 WWAN card
455 device ref shared_sram on end
456 device ref heci1 on end
457 device ref pmc hidden end
458 device ref emmc on end
459 device ref uart0 on end
460 device ref pch_espi on
461 chip ec/google/chromeec
462 device pnp 0c09.0 on end
463 end
464 end
465 device ref hda on
466 chip drivers/sof
467 register "spkr_tplg" = "max98360a"
468 register "jack_tplg" = "rt5682"
469 register "mic_tplg" = "_2ch_pdm0"
470 device generic 0 on end
471 end
472 end
473 end
474 end
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