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util/crossgcc/buildgcc: Add riscv64-elf to targets
[coreboot.git] / src / mainboard / google / brya / variants / volmar / overridetree.cb
blob96935170f1d90222ed58fb64573391409fd1632c
1 fw_config
2 field DB_USB 0 3
3 option USB_ABSENT 0
4 option USB3_PS8815 1
5 end
6 field KB_BL 4 4
7 option KB_BL_ABSENT 0
8 option KB_BL_PRESENT 1
9 end
10 field AUDIO 5 7
11 option AUDIO_UNKNOWN 0
12 option MAX98373_NAU88L25B_I2S 1
13 end
14 field BOOT_NVME_MASK 8
15 option BOOT_NVME_DISABLED 0
16 option BOOT_NVME_ENABLED 1
17 end
18 field BOOT_EMMC_MASK 9
19 option BOOT_EMMC_DISABLED 0
20 option BOOT_EMMC_ENABLED 1
21 end
22 field FPMCU_MASK 10
23 option FPMCU_ENABLED 0
24 option FPMCU_DISABLED 1
25 end
26 end
27 chip soc/intel/alderlake
28 register "sagv" = "SaGv_Enabled"
29
30 # As per Intel Advisory doc#723158, the change is required to prevent possible
31 # display flickering issue.
32 register "usb2_phy_sus_pg_disable" = "1"
33
34 register "tcss_aux_ori" = "1"
35 register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
36
37 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
38 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
39
40 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
41
42 # FIVR configurations are disabled since the board doesn't have V1p05 and Vnn
43 # bypass rails implemented.
44 register "ext_fivr_settings" = "{
45 .configure_ext_fivr = 1,
46 }"
47
48 # Intel Common SoC Config
49 #+-------------------+---------------------------+
50 #| Field | Value |
51 #+-------------------+---------------------------+
52 #| GSPI1 | Fingerprint MCU |
53 #| I2C0 | Audio |
54 #| I2C1 | cr50 TPM. Early init is |
55 #| | required to set up a BAR |
56 #| | for TPM communication |
57 #| I2C3 | TouchScreen |
58 #| I2C5 | Trackpad |
59 #+-------------------+---------------------------+
60 register "common_soc_config" = "{
61 .i2c[0] = {
62 .speed = I2C_SPEED_FAST,
63 },
64 .i2c[1] = {
65 .early_init = 1,
66 .speed = I2C_SPEED_FAST,
67 .rise_time_ns = 550,
68 .fall_time_ns = 400,
69 .data_hold_time_ns = 50,
70 },
71 .i2c[2] = {
72 .speed = I2C_SPEED_FAST,
73 },
74 .i2c[3] = {
75 .speed = I2C_SPEED_FAST,
76 .rise_time_ns = 550,
77 .fall_time_ns = 400,
78 .data_hold_time_ns = 50,
79 },
80 .i2c[5] = {
81 .speed = I2C_SPEED_FAST,
82 },
83 }"
84
85 device domain 0 on
86 device ref tbt_pcie_rp0 off end
87 device ref tbt_pcie_rp1 off end
88 device ref tbt_pcie_rp2 off end
89 device ref tcss_dma0 off end
90 device ref tcss_dma1 off end
91 device ref igpu on
92 chip drivers/gfx/generic
93 register "device_count" = "6"
94 # DDIA for eDP
95 register "device[0].name" = ""LCD0""
96 # Internal panel on the first port of the graphics chip
97 register "device[0].type" = "panel"
98 # DDIB for HDMI
99 register "device[1].name" = ""DD01""
100 # TCP0 (DP-1) for port C0
101 register "device[2].name" = ""DD02""
102 register "device[2].use_pld" = "true"
103 register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
104 # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
105 register "device[3].name" = ""DD03""
106 # TCP2 (DP-3) for port C1
107 register "device[4].name" = ""DD04""
108 register "device[4].use_pld" = "true"
109 register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
110 # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
111 register "device[5].name" = ""DD05""
112 device generic 0 on end
113 end
114 end # Integrated Graphics Device
115 device ref dtt on
116 chip drivers/intel/dptf
117 ## sensor information
118 register "options.tsr[0].desc" = ""DRAM""
119 register "options.tsr[1].desc" = ""Soc""
120 register "options.tsr[2].desc" = ""Charger""
121
122 # TODO: below values are initial reference values only
123 ## Active Policy
124 register "policies.active" = "{
125 [0] = {
126 .target = DPTF_CPU,
127 .thresholds = {
128 TEMP_PCT(85, 90),
129 TEMP_PCT(75, 80),
130 TEMP_PCT(68, 70),
131 TEMP_PCT(62, 60),
132 TEMP_PCT(55, 50),
133 TEMP_PCT(50, 40),
134 TEMP_PCT(40, 30),
135 }
136 },
137 [1] = {
138 .target = DPTF_TEMP_SENSOR_1,
139 .thresholds = {
140 TEMP_PCT(60, 90),
141 TEMP_PCT(55, 80),
142 TEMP_PCT(52, 70),
143 TEMP_PCT(48, 60),
144 TEMP_PCT(44, 50),
145 TEMP_PCT(40, 40),
146 TEMP_PCT(36, 30),
147 }
148 }
149 }"
150
151 ## Passive Policy
152 register "policies.passive" = "{
153 [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
154 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000),
155 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000),
156 [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000),
157 }"
158
159 ## Critical Policy
160 register "policies.critical" = "{
161 [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
162 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
163 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
164 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
165 }"
166
167 register "controls.power_limits" = "{
168 .pl1 = {
169 .min_power = 18000,
170 .max_power = 28000,
171 .time_window_min = 28 * MSECS_PER_SEC,
172 .time_window_max = 32 * MSECS_PER_SEC,
173 .granularity = 200,
174 },
175 .pl2 = {
176 .min_power = 40000,
177 .max_power = 40000,
178 .time_window_min = 28 * MSECS_PER_SEC,
179 .time_window_max = 32 * MSECS_PER_SEC,
180 .granularity = 1000,
181 }
182 }"
183
184 ## Charger Performance Control (Control, mA)
185 register "controls.charger_perf" = "{
186 [0] = { 255, 1700 },
187 [1] = { 24, 1500 },
188 [2] = { 16, 1000 },
189 [3] = { 8, 500 }
190 }"
191
192 ## Fan Performance Control (Percent, Speed, Noise, Power)
193 register "controls.fan_perf" = "{
194 [0] = { 90, 6700, 220, 2200, },
195 [1] = { 80, 5800, 180, 1800, },
196 [2] = { 70, 5000, 145, 1450, },
197 [3] = { 60, 4900, 115, 1150, },
198 [4] = { 50, 3838, 90, 900, },
199 [5] = { 40, 2904, 55, 550, },
200 [6] = { 30, 2337, 30, 300, },
201 [7] = { 20, 1608, 15, 150, },
202 [8] = { 10, 800, 10, 100, },
203 [9] = { 0, 0, 0, 50, }
204 }"
205
206 ## Fan options
207 register "options.fan.fine_grained_control" = "true"
208 register "options.fan.step_size" = "2"
209
210 device generic 0 alias dptf_policy on end
211 end
212 end
213 device ref pcie4_0 on
214 # Enable CPU PCIE RP 1 using CLK 0
215 register "cpu_pcie_rp[CPU_RP(1)]" = "{
216 .clk_req = 0,
217 .clk_src = 0,
218 .flags = PCIE_RP_LTR | PCIE_RP_AER,
219 }"
220 probe BOOT_NVME_MASK BOOT_NVME_ENABLED
221 end
222 device ref cnvi_wifi on
223 chip drivers/wifi/generic
224 register "wake" = "GPE0_PME_B0"
225 device generic 0 on end
226 end
227 end
228 device ref i2c0 on
229 chip drivers/i2c/nau8825
230 register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
231 register "jkdet_enable" = "1"
232 register "jkdet_pull_enable" = "0"
233 register "jkdet_pull_up" = "0"
234 register "jkdet_polarity" = "1" # ActiveLow
235 register "vref_impedance" = "2" # 125kOhm
236 register "micbias_voltage" = "6" # 2.754
237 register "sar_threshold_num" = "4"
238 register "sar_threshold[0]" = "0x0C"
239 register "sar_threshold[1]" = "0x1C"
240 register "sar_threshold[2]" = "0x38"
241 register "sar_threshold[3]" = "0x60"
242 register "sar_hysteresis" = "1"
243 register "sar_voltage" = "0" # VDDA
244 register "sar_compare_time" = "0" # 500ns
245 register "sar_sampling_time" = "0" # 2us
246 register "short_key_debounce" = "2" # 100ms
247 register "jack_insert_debounce" = "7" # 512ms
248 register "jack_eject_debounce" = "7" # 512ms
249 device i2c 1a on
250 probe AUDIO MAX98373_NAU88L25B_I2S
251 end
252 end
253 chip drivers/i2c/max98373
254 register "vmon_slot_no" = "0"
255 register "imon_slot_no" = "1"
256 register "uid" = "0"
257 register "desc" = ""Right Speaker Amp""
258 register "name" = ""MAXR""
259 device i2c 31 on
260 probe AUDIO MAX98373_NAU88L25B_I2S
261 end
262 end
263 chip drivers/i2c/max98373
264 register "vmon_slot_no" = "2"
265 register "imon_slot_no" = "3"
266 register "uid" = "1"
267 register "desc" = ""Left Speaker Amp""
268 register "name" = ""MAXL""
269 device i2c 32 on
270 probe AUDIO MAX98373_NAU88L25B_I2S
271 end
272 end
273 end #I2C0
274 device ref i2c1 on
275 chip drivers/i2c/tpm
276 register "hid" = ""GOOG0005""
277 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
278 device i2c 50 on end
279 end
280 end
281 device ref i2c3 on
282 chip drivers/i2c/hid
283 register "generic.hid" = ""ELAN90FC""
284 register "generic.desc" = ""ELAN Touchscreen""
285 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
286 register "generic.detect" = "1"
287 register "generic.reset_gpio" =
288 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
289 register "generic.reset_delay_ms" = "150"
290 register "generic.reset_off_delay_ms" = "1"
291 register "generic.enable_gpio" =
292 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
293 register "generic.enable_delay_ms" = "6"
294 register "generic.stop_gpio" =
295 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
296 register "generic.stop_off_delay_ms" = "1"
297 register "generic.has_power_resource" = "1"
298 register "hid_desc_reg_offset" = "0x01"
299 device i2c 0x10 on end
300 end
301 end
302 device ref i2c5 on
303 chip drivers/i2c/generic
304 register "hid" = ""ELAN0000""
305 register "desc" = ""ELAN Touchpad""
306 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
307 register "wake" = "GPE0_DW2_14"
308 register "detect" = "1"
309 device i2c 15 on end
310 end
311 chip drivers/i2c/hid
312 register "generic.hid" = ""SYNA0000""
313 register "generic.cid" = ""ACPI0C50""
314 register "generic.desc" = ""Synaptics Touchpad""
315 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
316 register "generic.wake" = "GPE0_DW2_14"
317 register "generic.detect" = "1"
318 register "hid_desc_reg_offset" = "0x20"
319 device i2c 0x2c on end
320 end
321 end
322 device ref pcie_rp3 on
323 chip soc/intel/common/block/pcie/rtd3
324 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
325 register "srcclk_pin" = "4"
326 register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
327 device generic 0 alias emmc_rtd3 on end
328 end
329 # Enable PCIe-to-eMMC bridge PCIE 3 using clk 4
330 register "pch_pcie_rp[PCH_RP(3)]" = "{
331 .clk_src = 4,
332 .clk_req = 4,
333 .flags = PCIE_RP_LTR | PCIE_RP_AER,
334 }"
335 probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
336 end #PCIE3 BH799BB
337 device ref pcie_rp6 off end # PCIE6 WWAN
338 device ref pcie_rp8 off end # PCIE8 SD card
339 device ref pcie_rp9 off end # PCIE9-12 SSD
340 device ref gspi1 on
341 chip drivers/spi/acpi
342 register "name" = ""CRFP""
343 register "hid" = "ACPI_DT_NAMESPACE_HID"
344 register "uid" = "1"
345 register "compat_string" = ""google,cros-ec-spi""
346 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
347 register "wake" = "GPE0_DW2_15"
348 register "has_power_resource" = "true"
349 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
350 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
351 register "enable_delay_ms" = "3"
352 device spi 0 on
353 probe FPMCU_MASK FPMCU_ENABLED
354 end
355 end # FPMCU
356 end
357 device ref pch_espi on
358 chip ec/google/chromeec
359 use conn0 as mux_conn[0]
360 use conn1 as mux_conn[1]
361 device pnp 0c09.0 on end
362 end
363 end
364 device ref pmc hidden
365 chip drivers/intel/pmc_mux
366 device generic 0 on
367 chip drivers/intel/pmc_mux/conn
368 use usb2_port1 as usb2_port
369 use tcss_usb3_port1 as usb3_port
370 device generic 0 alias conn0 on end
371 end
372 chip drivers/intel/pmc_mux/conn
373 use usb2_port3 as usb2_port
374 use tcss_usb3_port3 as usb3_port
375 device generic 1 alias conn1 on end
376 end
377 end
378 end
379 end
380 device ref tcss_xhci on
381 chip drivers/usb/acpi
382 device ref tcss_root_hub on
383 chip drivers/usb/acpi
384 register "desc" = ""USB3 Type-C Port C0 (MLB)""
385 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
386 register "use_custom_pld" = "true"
387 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
388 device ref tcss_usb3_port1 on end
389 end
390 chip drivers/usb/acpi
391 register "desc" = ""USB3 Type-C Port C1 (DB)""
392 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
393 register "use_custom_pld" = "true"
394 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
395 register "usb_lpm_incapable" = "true"
396 device ref tcss_usb3_port3 on end
397 end
398 end
399 end
400 end
401 device ref xhci on
402 chip drivers/usb/acpi
403 device ref xhci_root_hub on
404 chip drivers/usb/acpi
405 register "desc" = ""USB2 Type-C Port C0 (MLB)""
406 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
407 register "use_custom_pld" = "true"
408 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
409 device ref usb2_port1 on end
410 end
411 chip drivers/usb/acpi
412 register "desc" = ""USB2 Type-C Port C1 (DB)""
413 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
414 register "use_custom_pld" = "true"
415 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
416 device ref usb2_port3 on end
417 end
418 chip drivers/usb/acpi
419 register "desc" = ""USB2 Camera""
420 register "type" = "UPC_TYPE_INTERNAL"
421 device ref usb2_port6 on end
422 end
423 chip drivers/usb/acpi
424 register "desc" = ""USB2 Type-A Port A0 (DB)""
425 register "type" = "UPC_TYPE_A"
426 register "use_custom_pld" = "true"
427 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
428 device ref usb2_port9 on end
429 end
430 chip drivers/usb/acpi
431 register "desc" = ""USB2 Bluetooth""
432 register "type" = "UPC_TYPE_INTERNAL"
433 register "reset_gpio" =
434 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
435 device ref usb2_port10 on end
436 end
437 chip drivers/usb/acpi
438 register "desc" = ""USB3 Type-A Port A0 (DB)""
439 register "type" = "UPC_TYPE_USB3_A"
440 register "use_custom_pld" = "true"
441 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
442 device ref usb3_port1 on end
443 end
444 end
445 end
446 end
447 device ref hda on
448 chip drivers/sof
449 register "spkr_tplg" = "max98373"
450 register "jack_tplg" = "nau8825"
451 register "mic_tplg" = "_2ch_pdm0"
452 device generic 0 on end
453 end
454 end
455 end
456 end
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