src/mainboard/google/drallion/dsdt.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <variant/ec.h>
   4
   5 #include <acpi/acpi.h>
   6 DefinitionBlock(
   7         "dsdt.aml",
   8         "DSDT",
   9         ACPI_DSDT_REV_2,
  10         OEM_ID,
  11         ACPI_TABLE_CREATOR,
  12         0x20110725
  13 )
  14 {
  15         #include <acpi/dsdt_top.asl>
  16         #include <soc/intel/common/block/acpi/acpi/platform.asl>
  17         #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
  18         #include <cpu/intel/common/acpi/cpu.asl>
  19
  20         Scope (\_SB) {
  21                 Device (PCI0)
  22                 {
  23                         #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
  24                         #include <soc/intel/cannonlake/acpi/southbridge.asl>
  25                         #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
  26                 }
  27                 /* Per board variant mainboard hooks. */
  28                 #include <variant/acpi/mainboard.asl>
  29         }
  30
  31         #include <southbridge/intel/common/acpi/sleepstates.asl>
  32
  33         /* ChromeOS Embedded Controller */
  34         Scope (\_SB.PCI0.LPCB)
  35         {
  36                 /* ACPI code for EC SuperIO functions */
  37                 #include <ec/google/wilco/acpi/superio.asl>
  38                 /* ACPI code for EC functions */
  39                 #include <ec/google/wilco/acpi/ec.asl>
  40         }
  41
  42         /* Dynamic Platform Thermal Framework */
  43         Scope (\_SB)
  44         {
  45                 /* Per board variant specific definitions. */
  46                 #include <variant/acpi/dptf.asl>
  47                 /* Include common dptf ASL files */
  48                 #include <soc/intel/common/acpi/dptf/dptf.asl>
  49         }
  50 }