src/mainboard/google/fatcat/variants/felino/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/variants.h>
   4 #include <soc/romstage.h>
   5 #include <soc/meminit.h>
   6
   7 static const struct mb_cfg lp5_mem_config = {
   8         .type = MEM_TYPE_LP5X,
   9
  10         .lpx_dq_map = {
  11                 .ddr0 = {
  12                         .dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
  13                         .dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
  14                 },
  15                 .ddr1 = {
  16                         .dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
  17                         .dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
  18                 },
  19                 .ddr2 = {
  20                         .dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
  21                         .dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
  22                 },
  23                 .ddr3 = {
  24                         .dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
  25                         .dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
  26                 },
  27                 .ddr4 = {
  28                         .dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
  29                         .dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
  30                 },
  31                 .ddr5 = {
  32                         .dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
  33                         .dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
  34                 },
  35                 .ddr6 = {
  36                         .dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
  37                         .dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
  38                 },
  39                 .ddr7 = {
  40                         .dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
  41                         .dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
  42                 },
  43         },
  44
  45         .lpx_dqs_map = {
  46                 .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
  47                 .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
  48                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
  49                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
  50                 .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
  51                 .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
  52                 .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
  53                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 }
  54         },
  55
  56         .ect = true, /* Early Command Training */
  57
  58         .lp_ddr_dq_dqs_re_training = 1,
  59
  60         .user_bd = BOARD_TYPE_ULT_ULX,
  61
  62         .lp5x_config = {
  63                 .ccc_config = 0xFF,
  64         },
  65 };
  66
  67 const struct mb_cfg *variant_memory_params(void)
  68 {
  69         return &lp5_mem_config;
  70 }
  71
  72 void variant_get_spd_info(struct mem_spd *spd_info)
  73 {
  74         spd_info->topo = MEM_TOPO_MEMORY_DOWN;
  75         spd_info->cbfs_index = 0;
  76 }