src/mainboard/google/fatcat/variants/francka/fw_config.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/variants.h>
   4 #include <console/console.h>
   5 #include <fw_config.h>
   6 #include <gpio.h>
   7 #include <inttypes.h>
   8
   9 /* t: base table; o: override table */
  10 #define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
  11 /* t: table */
  12 #define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
  13
  14 static const struct pad_config hda_enable_pads[] = {
  15         /* HDA_BIT_CLK */
  16         PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
  17         /* HDA_SYNC */
  18         PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
  19         /* HDA_SDOUT */
  20         PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
  21         /* HDA_SDIN0 */
  22         PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
  23         /* SOC_DMIC_CLK1 */
  24         PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
  25         /* SOC_DMIC_DATA1 */
  26         PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
  27
  28         /* GPP_D09:     PCH_DGPU_HOLD_RST#_R */
  29         PAD_NC(GPP_D09, NONE),
  30         /* GPP_D16:     HDA_RST# */
  31         PAD_NC(GPP_D16, NONE),
  32         /* GPP_S00:     SNDW_3_SCL */
  33         PAD_NC(GPP_S00, NONE),
  34         /* GPP_S01:     SNDW_3_SDA */
  35         PAD_NC(GPP_S01, NONE),
  36         /* GPP_S02:     SOC_DMIC_CLK0 */
  37         PAD_NC(GPP_S02, NONE),
  38         /* GPP_S03:     SOC_DMIC_DATA0 */
  39         PAD_NC(GPP_S03, NONE),
  40         /* GPP_S04:     SNDW2_CLK */
  41         PAD_NC(GPP_S04, NONE),
  42         /* GPP_S05:     SNDW2_DATA0 */
  43         PAD_NC(GPP_S05, NONE),
  44 };
  45
  46 /*
  47  * WWAN: power sequence requires three stages:
  48  * step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off
  49  * step 2: deassert FCP#
  50  * step 3: deassert RST# first, and then PERST#.
  51  * NOTE: Since PERST# is gated by platform reset, PERST# deassertion will happen
  52  * at much later time and time between RST# and PERSET# is guaranteed.
  53  */
  54 static const struct pad_config pre_mem_wwan_pwr_seq1_pads[] = {
  55         /* GPP_A09:     SOC_WWAN_OFF#_SW */
  56         PAD_CFG_GPO(GPP_A09, 0, PLTRST),
  57         /* GPP_B20:     SOC_WWAN_RST# */
  58         PAD_CFG_GPO(GPP_B20, 0, PLTRST),
  59         /* GPP_D03:     SOC_WWAN_PCIE_RST# */
  60         PAD_CFG_GPO(GPP_D03, 0, PLTRST),
  61 };
  62
  63 static const struct pad_config pre_mem_wwan_pwr_seq2_pads[] = {
  64         /* GPP_A09:     SOC_WWAN_OFF#_SW */
  65         PAD_CFG_GPO(GPP_A09, 1, PLTRST),
  66 };
  67
  68 static const struct pad_config wwan_pwr_seq3_pads[] = {
  69         /* GPP_D03:     SOC_WWAN_PCIE_RST# */
  70         PAD_CFG_GPO(GPP_D03, 1, PLTRST),
  71         /* GPP_B20:     SOC_WWAN_RST# */
  72         PAD_CFG_GPO(GPP_B20, 1, PLTRST),
  73         /* GPP_E02:     SOC_WWAN_WAKE2#_R */
  74         PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
  75 };
  76
  77 static const struct pad_config wwan_disable_pads[] = {
  78         /* GPP_A09:     SOC_WWAN_OFF#_SW */
  79         PAD_NC(GPP_A09, NONE),
  80         /* GPP_D03:     SOC_WWAN_PCIE_RST#  */
  81         PAD_NC(GPP_D03, NONE),
  82         /* GPP_B20:     SOC_WWAN_RST# */
  83         PAD_NC(GPP_B20, NONE),
  84         /* GPP_A10:     SOC_WWAN_RA_DIS#_SW  */
  85         PAD_NC(GPP_A10, NONE),
  86         /* GPP_E02:     SOC_WWAN_WAKE2#_R */
  87         PAD_NC(GPP_E02, NONE),
  88 };
  89
  90 static const struct pad_config bridge_disable_pads[] = {
  91         /* GPP_D18:     CLKREQ_PCIE#6 */
  92         PAD_NC(GPP_D18, NONE),
  93 };
  94
  95 void fw_config_configure_pre_mem_gpio(void)
  96 {
  97         if (!fw_config_is_provisioned()) {
  98                 printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
  99                 return;
 100         }
 101
 102         if (!fw_config_probe(FW_CONFIG(WWAN, WWAN_ABSENT)))
 103                 GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads);
 104
 105         /*
 106          * NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM
 107          * FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V
 108          * and FCP#) is '0'. Therefore, it will be fine even though there is no
 109          * GPIO configured for other PADs via fw_config to have the time delay
 110          * introduced in between sequence 1 and 2. Also, FCP# was not the last PAD
 111          * configured in sequence 1. Although the Tpr is '0' in the datasheet, three
 112          * stages are preserved at this time to guarantee the sequence shown in the
 113          * datasheet timing diagram.
 114          */
 115         if (!fw_config_probe(FW_CONFIG(WWAN, WWAN_ABSENT)))
 116                 GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads);
 117 }
 118
 119 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 120 {
 121         if (!fw_config_is_provisioned()) {
 122                 printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
 123                 return;
 124         }
 125
 126         if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA)))
 127                 GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
 128
 129         if (fw_config_probe(FW_CONFIG(WWAN, WWAN_PRESENT))) {
 130                 GPIO_PADBASED_OVERRIDE(padbased_table, wwan_pwr_seq3_pads);
 131         } else {
 132                 GPIO_PADBASED_OVERRIDE(padbased_table, wwan_disable_pads);
 133         }
 134
 135         if (fw_config_probe(FW_CONFIG(BRIDGE, BRIDGE_HAYDEN))) {
 136                 GPIO_PADBASED_OVERRIDE(padbased_table, bridge_disable_pads);
 137         }
 138
 139 }