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device/pci_ids: Add Intel Panther Lake device IDs for Bluetooth CNVi
[coreboot.git] / src / mainboard / google / fizz / variants / baseboard / devicetree.cb
blob25114f055b8f103267e8f0d1875ea7d0074ae413
1 chip soc/intel/skylake
2
3 register "panel_cfg" = "{
4 .up_delay_ms = 200,
5 .down_delay_ms = 50,
6 .cycle_delay_ms = 500,
7 .backlight_on_delay_ms = 1,
8 .backlight_off_delay_ms = 200,
9 .backlight_pwm_hz = 200,
10 }"
11
12 # Deep Sx states
13 register "deep_s3_enable_ac" = "0"
14 register "deep_s3_enable_dc" = "0"
15 register "deep_s5_enable_ac" = "1"
16 register "deep_s5_enable_dc" = "1"
17 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
18
19 register "eist_enable" = "true"
20
21 # Mapping of USB port # to device
22 #+----------------+-------+-----------------------------------+
23 #| Device | Port# | Rev |
24 #+----------------+-------+-----------------------------------+
25 #| USB C | 1 | 2/3 |
26 #| USB A Rear | 2 | 2/3 |
27 #| USB A Front | 3 | 2/3 |
28 #| USB A Front | 4 | 2/3 |
29 #| USB A Rear | 5 | 2 on base celeron, 2/3 all others |
30 #| USB A Rear | 6 | 2 on base celeron, 2/3 all others |
31 #| Bluetooth | 7 | |
32 #| Daughter Board | 8 | |
33 #+----------------+-------+-----------------------------------+
34
35 # Bitmap for Wake Enable on USB attach/detach
36 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) |
37 USB_PORT_WAKE_ENABLE(3) |
38 USB_PORT_WAKE_ENABLE(4) |
39 USB_PORT_WAKE_ENABLE(5) |
40 USB_PORT_WAKE_ENABLE(6)"
41 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) |
42 USB_PORT_WAKE_ENABLE(3) |
43 USB_PORT_WAKE_ENABLE(4) |
44 USB_PORT_WAKE_ENABLE(5) |
45 USB_PORT_WAKE_ENABLE(6)"
46
47 # GPE configuration
48 # Note that GPE events called out in ASL code rely on this
49 # route. i.e. If this route changes then the affected GPE
50 # offset bits also need to be changed.
51 register "gpe0_dw0" = "GPP_B"
52 register "gpe0_dw1" = "GPP_D"
53 register "gpe0_dw2" = "GPP_E"
54
55 # Enable DPTF
56 register "dptf_enable" = "1"
57
58 # Enable S0ix
59 register "s0ix_enable" = true
60
61 # FSP Configuration
62 register "DspEnable" = "1"
63 register "IoBufferOwnership" = "3"
64 register "SkipExtGfxScan" = "1"
65 register "SaGv" = "SaGv_Enabled"
66 register "PmConfigSlpS3MinAssert" = "2" # 50ms
67 register "PmConfigSlpS4MinAssert" = "1" # 1s
68 register "PmConfigSlpSusMinAssert" = "1" # 500ms
69 register "PmConfigSlpAMinAssert" = "3" # 2s
70 register "SendVrMbxCmd" = "1" # IMVP8 workaround
71
72 # Intersil VR c-state issue workaround
73 # send VR mailbox command for IA/GT/SA rails
74 register "IslVrCmd" = "2"
75
76 # VR Settings Configuration for 4 Domains
77 #+----------------+-------+-------+-------+-------+
78 #| Domain/Setting | SA | IA | GTUS | GTS |
79 #+----------------+-------+-------+-------+-------+
80 #| Psi1Threshold | 20A | 20A | 20A | 20A |
81 #| Psi2Threshold | 4A | 5A | 5A | 5A |
82 #| Psi3Threshold | 1A | 1A | 1A | 1A |
83 #| Psi3Enable | 1 | 1 | 1 | 1 |
84 #| Psi4Enable | 1 | 1 | 1 | 1 |
85 #| ImonSlope | 0 | 0 | 0 | 0 |
86 #| ImonOffset | 0 | 0 | 0 | 0 |
87 #| IccMax | 7A | 34A | 35A | 35A |
88 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
89 #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
90 #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
91 #+----------------+-------+-------+-------+-------+
92 #Note: IccMax settings are moved to SoC code
93 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
94 .vr_config_enable = 1,
95 .psi1threshold = VR_CFG_AMP(20),
96 .psi2threshold = VR_CFG_AMP(4),
97 .psi3threshold = VR_CFG_AMP(1),
98 .psi3enable = 1,
99 .psi4enable = 1,
100 .imon_slope = 0x0,
101 .imon_offset = 0x0,
102 .voltage_limit = 1520,
103 .ac_loadline = 1030,
104 .dc_loadline = 1030,
105 }"
106
107 register "domain_vr_config[VR_IA_CORE]" = "{
108 .vr_config_enable = 1,
109 .psi1threshold = VR_CFG_AMP(20),
110 .psi2threshold = VR_CFG_AMP(5),
111 .psi3threshold = VR_CFG_AMP(1),
112 .psi3enable = 1,
113 .psi4enable = 1,
114 .imon_slope = 0x0,
115 .imon_offset = 0x0,
116 .voltage_limit = 1520,
117 .ac_loadline = 240,
118 .dc_loadline = 240,
119 }"
120
121 register "domain_vr_config[VR_GT_UNSLICED]" = "{
122 .vr_config_enable = 1,
123 .psi1threshold = VR_CFG_AMP(20),
124 .psi2threshold = VR_CFG_AMP(5),
125 .psi3threshold = VR_CFG_AMP(1),
126 .psi3enable = 1,
127 .psi4enable = 1,
128 .imon_slope = 0x0,
129 .imon_offset = 0x0,
130 .voltage_limit = 1520,
131 .ac_loadline = 310,
132 .dc_loadline = 310,
133 }"
134
135 register "domain_vr_config[VR_GT_SLICED]" = "{
136 .vr_config_enable = 1,
137 .psi1threshold = VR_CFG_AMP(20),
138 .psi2threshold = VR_CFG_AMP(5),
139 .psi3threshold = VR_CFG_AMP(1),
140 .psi3enable = 1,
141 .psi4enable = 1,
142 .imon_slope = 0x0,
143 .imon_offset = 0x0,
144 .voltage_limit = 1520,
145 .ac_loadline = 310,
146 .dc_loadline = 310,
147 }"
148
149
150 register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC
151 register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
152 register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug
153 register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
154
155 # Intel Common SoC Config
156 #+-------------------+---------------------------+
157 #| Field | Value |
158 #+-------------------+---------------------------+
159 #| GSPI0 | cr50 TPM. Early init is |
160 #| | required to set up a BAR |
161 #| | for TPM communication |
162 #| | before memory is up |
163 #| I2C5 | Audio |
164 #+-------------------+---------------------------+
165
166 register "common_soc_config" = "{
167 .gspi[0] = {
168 .speed_mhz = 1,
169 .early_init = 1,
170 },
171 .i2c[5] = {
172 .speed = I2C_SPEED_FAST,
173 .speed_config[0] = {
174 .speed = I2C_SPEED_FAST,
175 .scl_lcnt = 194,
176 .scl_hcnt = 100,
177 .sda_hold = 36,
178 },
179 },
180 }"
181
182 # Must leave UART0 enabled or SD/eMMC will not work as PCI
183 register "SerialIoDevMode" = "{
184 [PchSerialIoIndexI2C0] = PchSerialIoPci,
185 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
186 [PchSerialIoIndexI2C2] = PchSerialIoPci,
187 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
188 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
189 [PchSerialIoIndexI2C5] = PchSerialIoPci,
190 [PchSerialIoIndexSpi0] = PchSerialIoPci,
191 [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
192 [PchSerialIoIndexUart0] = PchSerialIoSkipInit,
193 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
194 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
195 }"
196
197 register "power_limits_config" = "{
198 .tdp_psyspl2 = 90,
199 .psys_pmax = 120,
200 }"
201 register "tcc_offset" = "6" # TCC of 94C
202
203 device domain 0 on
204 device ref igpu on end
205 device ref sa_thermal on end
206 device ref south_xhci on
207 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C
208 register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear
209 register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front
210 register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front
211 register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear
212 register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear
213 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
214 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug
215
216 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C
217 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear
218 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
219 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
220 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
221 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
222
223 chip drivers/usb/acpi
224 register "desc" = ""Root Hub""
225 register "type" = "UPC_TYPE_HUB"
226 device usb 0.0 on
227 chip drivers/usb/acpi
228 register "desc" = ""USB2 Type-C Rear""
229 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
230 device usb 2.0 on end
231 end
232 chip drivers/usb/acpi
233 register "desc" = ""USB2 Type-A Rear Left""
234 register "type" = "UPC_TYPE_A"
235 device usb 2.1 on end
236 end
237 chip drivers/usb/acpi
238 register "desc" = ""USB2 Type-A Rear Right""
239 register "type" = "UPC_TYPE_A"
240 device usb 2.4 on end
241 end
242 chip drivers/usb/acpi
243 register "desc" = ""USB2 Type-A Rear Middle""
244 register "type" = "UPC_TYPE_A"
245 device usb 2.5 on end
246 end
247 chip drivers/usb/acpi
248 register "desc" = ""USB2 Bluetooth""
249 register "type" = "UPC_TYPE_INTERNAL"
250 device usb 2.6 on end
251 end
252 chip drivers/usb/acpi
253 register "desc" = ""USB3 Type-C Rear""
254 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
255 device usb 3.0 on end
256 end
257 chip drivers/usb/acpi
258 register "desc" = ""USB3 Type-A Rear Left""
259 register "type" = "UPC_TYPE_USB3_A"
260 device usb 3.1 on end
261 end
262 chip drivers/usb/acpi
263 register "desc" = ""USB3 Type-A Rear Right""
264 register "type" = "UPC_TYPE_USB3_A"
265 device usb 3.4 on end
266 end
267 chip drivers/usb/acpi
268 register "desc" = ""USB3 Type-A Rear Middle""
269 register "type" = "UPC_TYPE_USB3_A"
270 device usb 3.5 on end
271 end
272 end
273 end
274 end
275 device ref thermal on end
276 device ref i2c0 on end
277 device ref i2c2 on end
278 device ref heci1 on end
279 device ref sata on
280 register "SataPortsEnable" = "{
281 [0] = 1,
282 [1] = 1,
283 }"
284 register "SataPortsDevSlp[1]" = "1"
285 end
286 device ref uart2 on end
287 device ref i2c5 on end
288 device ref pcie_rp1 on end
289 device ref pcie_rp3 on
290 # LAN, will be swapped to port 1 by FSP
291 # x1
292 register "PcieRpEnable[2]" = "1"
293 register "PcieRpClkReqSupport[2]" = "1"
294 register "PcieRpClkReqNumber[2]" = "0"
295 register "PcieRpAdvancedErrorReporting[2]" = "1"
296 register "PcieRpLtrEnable[2]" = "1"
297 register "PcieRpClkSrcNumber[2]" = "0"
298 chip drivers/net
299 register "customized_leds" = "0x0fa5"
300 register "wake" = "GPE0_PCI_EXP"
301 device pci 00.0 on end
302 register "device_index" = "0"
303 end
304 end
305 device ref pcie_rp4 on
306 # x1 WLAN
307 register "PcieRpEnable[3]" = "1"
308 register "PcieRpClkReqSupport[3]" = "1"
309 register "PcieRpClkReqNumber[3]" = "5"
310 register "PcieRpAdvancedErrorReporting[3]" = "1"
311 register "PcieRpLtrEnable[3]" = "1"
312 register "PcieRpClkSrcNumber[3]" = "5"
313 chip drivers/wifi/generic
314 register "wake" = "GPE0_PCI_EXP"
315 device pci 00.0 on end
316 end
317 end
318 device ref pcie_rp5 on
319 # x4 NVMe
320 register "PcieRpEnable[4]" = "1"
321 register "PcieRpClkReqSupport[4]" = "1"
322 register "PcieRpClkReqNumber[4]" = "1"
323 register "PcieRpAdvancedErrorReporting[4]" = "1"
324 register "PcieRpLtrEnable[4]" = "1"
325 register "PcieRpClkSrcNumber[4]" = "1"
326 end
327 device ref pcie_rp9 on
328 # 2nd LAN
329 register "PcieRpEnable[8]" = "1"
330 register "PcieRpClkReqSupport[8]" = "1"
331 register "PcieRpClkReqNumber[8]" = "2"
332 register "PcieRpAdvancedErrorReporting[8]" = "1"
333 register "PcieRpLtrEnable[8]" = "1"
334 register "PcieRpClkSrcNumber[8]" = "2"
335 chip drivers/net
336 register "customized_leds" = "0x0fa5"
337 register "device_index" = "1"
338 device pci 00.0 on end
339 end
340 end
341 device ref pcie_rp11 on
342 register "PcieRpEnable[10]" = "1"
343 register "PcieRpClkReqSupport[10]" = "1"
344 register "PcieRpClkReqNumber[10]" = "2"
345 register "PcieRpAdvancedErrorReporting[10]" = "1"
346 register "PcieRpLtrEnable[10]" = "1"
347 register "PcieRpClkSrcNumber[10]" = "2"
348 end
349 device ref pcie_rp12 on
350 register "PcieRpEnable[11]" = "1"
351 register "PcieRpClkReqSupport[11]" = "1"
352 register "PcieRpClkReqNumber[11]" = "2"
353 register "PcieRpAdvancedErrorReporting[11]" = "1"
354 register "PcieRpLtrEnable[11]" = "1"
355 register "PcieRpClkSrcNumber[11]" = "2"
356 end
357 device ref uart0 on end
358 device ref gspi0 on
359 chip drivers/spi/acpi
360 register "hid" = "ACPI_DT_NAMESPACE_HID"
361 register "compat_string" = ""google,cr50""
362 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
363 device spi 0 on end
364 end
365 end
366 device ref sdxc on end
367 device ref lpc_espi on
368 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
369 register "gen1_dec" = "0x00fc0801"
370 register "gen2_dec" = "0x000c0201"
371 # EC memory map range is 0x900-0x9ff
372 register "gen3_dec" = "0x00fc0901"
373
374 chip ec/google/chromeec
375 device pnp 0c09.0 on end
376 end
377 end
378 device ref hda on end
379 device ref smbus on end
380 device ref fast_spi on end
381 end
382 end
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