soc/intel/common: Simply code accessing scaling factors
[coreboot.git] / src / mainboard / google / gale / mainboard.c
blob3c4f86184e3a27db542d407bbe9d7592c003017a
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <boot/coreboot_tables.h>
4 #include <device/device.h>
5 #include <gpio.h>
6 #include <soc/clock.h>
7 #include <soc/soc_services.h>
8 #include <soc/usb.h>
9 #include <soc/blsp.h>
10 #include <symbols.h>
12 #include <vendorcode/google/chromeos/chromeos.h>
13 #include "mmu.h"
15 #define USB_ENABLE_GPIO 51
17 static void setup_usb(void)
19 usb_clock_config();
21 setup_usb_host1();
24 static void mainboard_init(struct device *dev)
26 /* disable mmu and d-cache before setting up secure world.*/
27 dcache_mmu_disable();
28 start_tzbsp();
29 /* Setup mmu and d-cache again as non secure entries. */
30 setup_mmu(DRAM_INITIALIZED);
31 setup_usb();
33 /* Copy WIFI calibration data into CBMEM. */
34 if (CONFIG(CHROMEOS))
35 cbmem_add_vpd_calibration_data();
38 * Make sure bootloader can issue sounds The frequency is calculated
39 * as "<frame_rate> * <bit_width> * <channels> * 4", i.e.
41 * 48000 * 2 * 16 * 4 = 6144000
43 //audio_clock_config(6144000);
46 static void mainboard_enable(struct device *dev)
48 dev->ops->init = &mainboard_init;
51 struct chip_operations mainboard_ops = {
52 .enable_dev = mainboard_enable,
55 void lb_board(struct lb_header *header)
57 struct lb_range *dma;
59 dma = (struct lb_range *)lb_new_record(header);
60 dma->tag = LB_TAG_DMA;
61 dma->size = sizeof(*dma);
62 dma->range_start = (uintptr_t)_dma_coherent;
63 dma->range_size = REGION_SIZE(dma_coherent);
65 if (CONFIG(CHROMEOS)) {
66 /* Retrieve the switch interface MAC addresses. */
67 lb_table_add_macs_from_vpd(header);