src/mainboard/google/guybrush/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpigen.h>
   5 #include <amdblocks/acpi.h>
   6 #include <amdblocks/acpimmio.h>
   7 #include <amdblocks/amd_pci_util.h>
   8 #include <amdblocks/psp.h>
   9 #include <amdblocks/xhci.h>
  10 #include <baseboard/variants.h>
  11 #include <cpu/x86/smm.h>
  12 #include <device/device.h>
  13 #include <drivers/i2c/tpm/chip.h>
  14 #include <gpio.h>
  15 #include <static.h>
  16 #include <variant/ec.h>
  17
  18 #define BACKLIGHT_GPIO                  GPIO_129
  19 #define WWAN_AUX_RST_GPIO               GPIO_18
  20 #define METHOD_BACKLIGHT_ENABLE         "\\_SB.BKEN"
  21 #define METHOD_BACKLIGHT_DISABLE        "\\_SB.BKDS"
  22 #define METHOD_MAINBOARD_INI            "\\_SB.MINI"
  23 #define METHOD_MAINBOARD_WAK            "\\_SB.MWAK"
  24 #define METHOD_MAINBOARD_PTS            "\\_SB.MPTS"
  25 #define METHOD_MAINBOARD_S0X            "\\_SB.MS0X"
  26
  27 /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
  28    accessed via I/O ports 0xc00/0xc01. */
  29
  30 /*
  31  * This controls the device -> IRQ routing.
  32  *
  33  * Hardcoded IRQs:
  34  *  0: timer < soc/amd/common/acpi/lpc.asl
  35  *  1: i8042 - Keyboard
  36  *  2: cascade
  37  *  8: rtc0 <- soc/amd/common/acpi/lpc.asl
  38  *  9: acpi <- soc/amd/common/acpi/lpc.asl
  39  */
  40 static const struct fch_irq_routing fch_irq_map[] = {
  41         { PIRQ_A,       12,             PIRQ_NC },
  42         { PIRQ_B,       14,             PIRQ_NC },
  43         { PIRQ_C,       15,             PIRQ_NC },
  44         { PIRQ_D,       12,             PIRQ_NC },
  45         { PIRQ_E,       14,             PIRQ_NC },
  46         { PIRQ_F,       15,             PIRQ_NC },
  47         { PIRQ_G,       12,             PIRQ_NC },
  48         { PIRQ_H,       14,             PIRQ_NC },
  49
  50         { PIRQ_SCI,     ACPI_SCI_IRQ,   ACPI_SCI_IRQ },
  51         { PIRQ_SD,      PIRQ_NC,        PIRQ_NC },
  52         { PIRQ_SDIO,    PIRQ_NC,        PIRQ_NC },
  53         { PIRQ_SATA,    PIRQ_NC,        PIRQ_NC },
  54         { PIRQ_EMMC,    PIRQ_NC,        PIRQ_NC },
  55         { PIRQ_GPIO,    11,             11 },
  56         { PIRQ_I2C0,    10,             10 },
  57         { PIRQ_I2C1,     7,              7 },
  58         { PIRQ_I2C2,     6,              6 },
  59         { PIRQ_I2C3,     5,              5 },
  60         { PIRQ_UART0,    4,              4 },
  61         { PIRQ_UART1,    3,              3 },
  62
  63         /* The MISC registers are not interrupt numbers */
  64         { PIRQ_MISC,    0xfa,           0x00 },
  65         { PIRQ_MISC0,   0x91,           0x00 },
  66         { PIRQ_HPET_L,  0x00,           0x00 },
  67         { PIRQ_HPET_H,  0x00,           0x00 },
  68 };
  69
  70 const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
  71 {
  72         *length = ARRAY_SIZE(fch_irq_map);
  73         return fch_irq_map;
  74 }
  75
  76 static void mainboard_configure_gpios(void)
  77 {
  78         size_t base_num_gpios, override_num_gpios;
  79         const struct soc_amd_gpio *base_gpios, *override_gpios;
  80
  81         base_gpios = baseboard_gpio_table(&base_num_gpios);
  82         override_gpios = variant_override_gpio_table(&override_num_gpios);
  83
  84         gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios,
  85                                           override_num_gpios);
  86 }
  87
  88 void __weak variant_devtree_update(void)
  89 {
  90 }
  91
  92 static void configure_psp_tpm_gpio(void)
  93 {
  94         const struct device *cr50_dev = DEV_PTR(cr50);
  95         struct drivers_i2c_tpm_config *cfg = config_of(cr50_dev);
  96
  97         psp_set_tpm_irq_gpio(cfg->irq_gpio.pins[0]);
  98 }
  99
 100 static void mainboard_init(void *chip_info)
 101 {
 102         mainboard_configure_gpios();
 103         mainboard_ec_init();
 104         variant_devtree_update();
 105
 106         /* Run this after variant_devtree_update so the IRQ is correct. */
 107         configure_psp_tpm_gpio();
 108 }
 109
 110 static void mainboard_write_blken(void)
 111 {
 112         acpigen_write_method(METHOD_BACKLIGHT_ENABLE, 0);
 113         acpigen_soc_clear_tx_gpio(BACKLIGHT_GPIO);
 114         acpigen_pop_len();
 115 }
 116
 117 static void mainboard_write_blkdis(void)
 118 {
 119         acpigen_write_method(METHOD_BACKLIGHT_DISABLE, 0);
 120         acpigen_soc_set_tx_gpio(BACKLIGHT_GPIO);
 121         acpigen_pop_len();
 122 }
 123
 124 static void mainboard_write_mini(void)
 125 {
 126         acpigen_write_method(METHOD_MAINBOARD_INI, 0);
 127         acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE);
 128         acpigen_pop_len();
 129 }
 130
 131 static void mainboard_write_mwak(void)
 132 {
 133         acpigen_write_method(METHOD_MAINBOARD_WAK, 0);
 134         acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE);
 135         acpigen_pop_len();
 136 }
 137
 138 static void mainboard_write_mpts(void)
 139 {
 140         acpigen_write_method(METHOD_MAINBOARD_PTS, 0);
 141         acpigen_emit_namestring(METHOD_BACKLIGHT_DISABLE);
 142         acpigen_pop_len();
 143 }
 144
 145 static void mainboard_assert_wwan_aux_reset(void)
 146 {
 147         if (variant_has_pcie_wwan())
 148                 acpigen_soc_clear_tx_gpio(WWAN_AUX_RST_GPIO);
 149 }
 150
 151 static void mainboard_deassert_wwan_aux_reset(void)
 152 {
 153         if (variant_has_pcie_wwan())
 154                 acpigen_soc_set_tx_gpio(WWAN_AUX_RST_GPIO);
 155 }
 156
 157 static void mainboard_write_ms0x(void)
 158 {
 159         acpigen_write_method_serialized(METHOD_MAINBOARD_S0X, 1);
 160         /* S0ix Entry */
 161         acpigen_write_if_lequal_op_int(ARG0_OP, 1);
 162         mainboard_assert_wwan_aux_reset();
 163         /* S0ix Exit */
 164         acpigen_write_else();
 165         mainboard_deassert_wwan_aux_reset();
 166         acpigen_pop_len();
 167         acpigen_pop_len();
 168 }
 169
 170 static void mainboard_fill_ssdt(const struct device *dev)
 171 {
 172         mainboard_write_blken();
 173         mainboard_write_blkdis();
 174         mainboard_write_mini();
 175         mainboard_write_mpts();
 176         mainboard_write_mwak();
 177         mainboard_write_ms0x();
 178 }
 179
 180 static void mainboard_enable(struct device *dev)
 181 {
 182         dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 183
 184         /* TODO: b/184678786 - Move into espi_config */
 185         /* Unmask eSPI IRQ 1 (Keyboard) */
 186         pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
 187 }
 188
 189 void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
 190 {
 191         soc_xhci_store_resources(slots, size);
 192 }
 193
 194 struct chip_operations mainboard_ops = {
 195         .init = mainboard_init,
 196         .enable_dev = mainboard_enable,
 197 };