src/mainboard/google/guybrush/variants/baseboard/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2 chip soc/amd/cezanne
   3
   4         register "common_config.acp_config" = "{
   5                 .acp_pin_cfg = I2S_PINS_I2S_TDM,
   6                 .acp_i2s_wake_enable = 0,
   7                 .acp_pme_enable = 0,
   8                 .dmic_present = 1,
   9         }"
  10
  11         # eSPI Configuration
  12         register "common_config.espi_config" = "{
  13                 .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN,
  14                 .generic_io_range[0] = {
  15                         .base = 0x62,
  16                         /*
  17                          * Only 0x62 and 0x66 are required. But, this is not supported by
  18                          * standard IO decodes and there are only 4 generic I/O windows
  19                          * available. Hence, open a window from 0x62-0x67.
  20                          */
  21                         .size = 5,
  22                 },
  23                 .generic_io_range[1] = {
  24                         .base = 0x800,   /* EC_HOST_CMD_REGION0 */
  25                         .size = 256,     /* EC_HOST_CMD_REGION_SIZE * 2 */
  26                 },
  27                 .generic_io_range[2] = {
  28                         .base = 0x900,   /* EC_LPC_ADDR_MEMMAP */
  29                         .size = 255,     /* EC_MEMMAP_SIZE */
  30                 },
  31                 .generic_io_range[3] = {
  32                         .base = 0x200,   /* EC_LPC_ADDR_HOST_DATA */
  33                         .size = 8,       /* 0x200 - 0x207 */
  34                 },
  35
  36                 .io_mode = ESPI_IO_MODE_QUAD,
  37                 .op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
  38                 .crc_check_enable = 1,
  39                 .alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN,
  40                 .periph_ch_en = 1,
  41                 .vw_ch_en = 1,
  42                 .oob_ch_en = 0,
  43                 .flash_ch_en = 0,
  44
  45                 /*
  46                  * b/218874489 - This should really be ESPI_VW_IRQ_LEVEL_HIGH,
  47                  * but eSPI gets configured in verstage which is in RO, and the
  48                  * RO is already locked down. As a workaround, the EC fw has
  49                  * been modified to use active low signalling for the
  50                  * interrupts that require it.
  51                  */
  52                 .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1),
  53         }"
  54
  55         # Enable S0i3 support
  56         register "s0ix_enable" = "true"
  57
  58         # Enable STT support
  59         register "stt_control" = "1"
  60         register "stt_pcb_sensor_count" = "2"
  61         register "stt_min_limit" = "0"
  62         register "stt_m1" = "0x03A0"
  63         register "stt_m2" = "0xFFC9"
  64         register "stt_m3" = "0"
  65         register "stt_m4" = "0"
  66         register "stt_m5" = "0"
  67         register "stt_m6" = "0"
  68         register "stt_c_apu" = "0x0901"
  69         register "stt_c_gpu" = "0"
  70         register "stt_c_hs2" = "0"
  71         register "stt_alpha_apu" = "0x199A"
  72         register "stt_alpha_gpu" = "0"
  73         register "stt_alpha_hs2" = "0"
  74         register "stt_skin_temp_apu" = "0x2D00"
  75         register "stt_skin_temp_gpu" = "0"
  76         register "stt_skin_temp_hs2" = "0"
  77         register "stt_error_coeff" = "0x21"
  78         register "stt_error_rate_coefficient" = "0xCCD"
  79
  80         register "system_configuration" = "2"
  81
  82         register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
  83                                         GPIO_I2C2_SCL | GPIO_I2C3_SCL"
  84         # I2C Pad Control RX Select Configuration
  85         register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" # Trackpad
  86         register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" # Touchscreen
  87         register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" # Audio/SAR
  88         register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC
  89
  90         # general purpose PCIe clock output configuration
  91         register "gpp_clk_config[0]" = "GPP_CLK_REQ"
  92         register "gpp_clk_config[1]" = "GPP_CLK_REQ"
  93         register "gpp_clk_config[2]" = "GPP_CLK_REQ"
  94         register "gpp_clk_config[3]" = "GPP_CLK_REQ"
  95         register "gpp_clk_config[4]" = "GPP_CLK_OFF"
  96         register "gpp_clk_config[5]" = "GPP_CLK_OFF"
  97         register "gpp_clk_config[6]" = "GPP_CLK_OFF"
  98
  99         register "pspp_policy" = "DXIO_PSPP_BALANCED"
 100
 101         register "usb_phy_custom" = "true"
 102         register "usb_phy" = "{
 103                 /* Left USB C0 Port */
 104                 .Usb2PhyPort[0] = {
 105                         .compdstune = 3,
 106                         .sqrxtune = 3,
 107                         .txfslstune = 3,
 108                         .txpreempamptune = 1,
 109                         .txpreemppulsetune = 0,
 110                         .txrisetune = 1,
 111                         .txvreftune = 6,
 112                         .txhsxvtune = 3,
 113                         .txrestune = 1,
 114                 },
 115                 /* Left USB A0 Port or WWAN */
 116                 .Usb2PhyPort[1] = {
 117                         .compdstune = 3,
 118                         .sqrxtune = 3,
 119                         .txfslstune = 3,
 120                         .txpreempamptune = 1,
 121                         .txpreemppulsetune = 0,
 122                         .txrisetune = 1,
 123                         .txvreftune = 6,
 124                         .txhsxvtune = 3,
 125                         .txrestune = 1,
 126                 },
 127                 /* User facing camera */
 128                 .Usb2PhyPort[2] = {
 129                         .compdstune = 1,
 130                         .sqrxtune = 3,
 131                         .txfslstune = 3,
 132                         .txpreempamptune = 2,
 133                         .txpreemppulsetune = 0,
 134                         .txrisetune = 2,
 135                         .txvreftune = 3,
 136                         .txhsxvtune = 3,
 137                         .txrestune = 2,
 138                 },
 139                 /* World facing camera */
 140                 .Usb2PhyPort[3] = {
 141                         .compdstune = 1,
 142                         .sqrxtune = 3,
 143                         .txfslstune = 3,
 144                         .txpreempamptune = 2,
 145                         .txpreemppulsetune = 0,
 146                         .txrisetune = 2,
 147                         .txvreftune = 3,
 148                         .txhsxvtune = 3,
 149                         .txrestune = 2,
 150                 },
 151                 /* Right USB C1 Port */
 152                 .Usb2PhyPort[4] = {
 153                         .compdstune = 3,
 154                         .sqrxtune = 3,
 155                         .txfslstune = 3,
 156                         .txpreempamptune = 1,
 157                         .txpreemppulsetune = 0,
 158                         .txrisetune = 1,
 159                         .txvreftune = 6,
 160                         .txhsxvtune = 3,
 161                         .txrestune = 1,
 162                 },
 163                 /* Right USB A1 Port */
 164                 .Usb2PhyPort[5] = {
 165                         .compdstune = 5,
 166                         .sqrxtune = 3,
 167                         .txfslstune = 3,
 168                         .txpreempamptune = 1,
 169                         .txpreemppulsetune = 0,
 170                         .txrisetune = 1,
 171                         .txvreftune = 9,
 172                         .txhsxvtune = 3,
 173                         .txrestune = 1,
 174                 },
 175                 /* WiFi / Bluetooth */
 176                 .Usb2PhyPort[6] = {
 177                         .compdstune = 1,
 178                         .sqrxtune = 3,
 179                         .txfslstune = 3,
 180                         .txpreempamptune = 2,
 181                         .txpreemppulsetune = 0,
 182                         .txrisetune = 2,
 183                         .txvreftune = 3,
 184                         .txhsxvtune = 3,
 185                         .txrestune = 2,
 186                 },
 187                 /* Smart Card */
 188                 .Usb2PhyPort[7] = {
 189                         .compdstune = 1,
 190                         .sqrxtune = 3,
 191                         .txfslstune = 3,
 192                         .txpreempamptune = 2,
 193                         .txpreemppulsetune = 0,
 194                         .txrisetune = 2,
 195                         .txvreftune = 3,
 196                         .txhsxvtune = 3,
 197                         .txrestune = 2,
 198                 },
 199                 /* Left USB C0 Port */
 200                 .Usb3PhyPort[0] = {
 201                         .tx_term_ctrl=2,
 202                         .rx_term_ctrl=2,
 203                         .tx_vboost_lvl_en=1,
 204                         .tx_vboost_lvl=5,
 205                 },
 206                 /* Left USB A0 Port or WWAN */
 207                 .Usb3PhyPort[1] = {
 208                         .tx_term_ctrl=2,
 209                         .rx_term_ctrl=2,
 210                         .tx_vboost_lvl_en=1,
 211                         .tx_vboost_lvl=5,
 212                 },
 213                 /* Right USB C1 Port */
 214                 .Usb3PhyPort[2] = {
 215                         .tx_term_ctrl=2,
 216                         .rx_term_ctrl=2,
 217                         .tx_vboost_lvl_en=1,
 218                         .tx_vboost_lvl=5,
 219                 },
 220                 /* Right USB A1 Port */
 221                 .Usb3PhyPort[3] = {
 222                         .tx_term_ctrl=2,
 223                         .rx_term_ctrl=2,
 224                         .tx_vboost_lvl_en=1,
 225                         .tx_vboost_lvl=5,
 226                 },
 227                 .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
 228                 .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
 229                 .BatteryChargerEnable = 0,
 230                 .PhyP3CpmP4Support = 0,
 231         }"
 232
 233         device domain 0 on
 234                 device ref iommu on end
 235
 236                 device ref gpp_bridge_0 on
 237                         chip drivers/pcie/generic
 238                                 register "wake_gpe" = "GEVENT_8"
 239                                 register "wake_deepest" = "ACPI_S0"
 240                                 register "name" = ""WLAN""
 241                                 device pci 00.0 on end
 242                         end
 243                 end # WLAN
 244                 device ref gpp_bridge_1 on end # SD
 245                 device ref gpp_bridge_2 on end # WWAN
 246                 device ref gpp_bridge_3 on
 247                         # Required so the NVMe gets placed into D3 when entering S0i3.
 248                         chip drivers/pcie/rtd3/device
 249                                 register "name" = ""NVME""
 250                                 device pci 00.0 on end
 251                         end
 252                 end # NVMe
 253
 254                 device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 255                         device ref gfx on end # Internal GPU (GFX)
 256                         device ref gfx_hda on end # GFX HD Audio Controller
 257                         device ref crypto on end # Crypto Coprocessor
 258                         device ref xhci_0 on # USB 3.1 (USB0)
 259                                 chip drivers/usb/acpi
 260                                         device ref xhci_0_root_hub on
 261                                                 chip drivers/usb/acpi
 262                                                         register "desc" = ""Left Type-C Port""
 263                                                         register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 264                                                         register "use_custom_pld" = "true"
 265                                                         register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
 266                                                         device ref usb3_port0 on end
 267                                                 end
 268                                                 chip drivers/usb/acpi
 269                                                         register "desc" = ""Left Type-A Port""
 270                                                         register "type" = "UPC_TYPE_USB3_A"
 271                                                         register "use_custom_pld" = "true"
 272                                                         register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))"
 273                                                         device ref usb3_port1 on end
 274                                                 end
 275                                                 chip drivers/usb/acpi
 276                                                         register "desc" = ""Left Type-C Port""
 277                                                         register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 278                                                         register "use_custom_pld" = "true"
 279                                                         register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
 280                                                         device ref usb2_port0 on end
 281                                                 end
 282                                                 chip drivers/usb/acpi
 283                                                         register "desc" = ""Left Type-A Port""
 284                                                         register "type" = "UPC_TYPE_USB3_A"
 285                                                         register "use_custom_pld" = "true"
 286                                                         register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))"
 287                                                         device ref usb2_port1 on end
 288                                                 end
 289                                                 chip drivers/usb/acpi
 290                                                         register "desc" = ""User-Facing Camera""
 291                                                         register "type" = "UPC_TYPE_INTERNAL"
 292                                                         device ref usb2_port2 on end
 293                                                 end
 294                                                 chip drivers/usb/acpi
 295                                                         register "desc" = ""World-Facing Camera""
 296                                                         register "type" = "UPC_TYPE_INTERNAL"
 297                                                         device ref usb2_port3 on end
 298                                                 end
 299                                         end
 300                                 end
 301                         end
 302                         device ref xhci_1 on # USB 3.1 (USB1)
 303                                 chip drivers/usb/acpi
 304                                         device ref xhci_1_root_hub on
 305                                                 chip drivers/usb/acpi
 306                                                         register "desc" = ""Right Type-C Port""
 307                                                         register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 308                                                         register "use_custom_pld" = "true"
 309                                                         register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 2))"
 310                                                         device ref usb3_port4 on end
 311                                                 end
 312                                                 chip drivers/usb/acpi
 313                                                         register "desc" = ""Right Type-A Port""
 314                                                         register "type" = "UPC_TYPE_USB3_A"
 315                                                         register "use_custom_pld" = "true"
 316                                                         register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
 317                                                         device ref usb3_port5 on end
 318                                                 end
 319                                                 chip drivers/usb/acpi
 320                                                         register "desc" = ""Right Type-C Port""
 321                                                         register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 322                                                         register "use_custom_pld" = "true"
 323                                                         register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 2))"
 324                                                         device ref usb2_port4 on end
 325                                                 end
 326                                                 chip drivers/usb/acpi
 327                                                         register "desc" = ""Right Type-A Port""
 328                                                         register "type" = "UPC_TYPE_USB3_A"
 329                                                         register "use_custom_pld" = "true"
 330                                                         register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
 331                                                         device ref usb2_port5 on end
 332                                                 end
 333                                                 chip drivers/usb/acpi
 334                                                         register "desc" = ""Bluetooth""
 335                                                         register "type" = "UPC_TYPE_INTERNAL"
 336                                                         register "has_power_resource" = "true"
 337                                                         register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_132)"
 338                                                         register "enable_delay_ms" = "500"
 339                                                         register "enable_off_delay_ms" = "200"
 340                                                         register "use_gpio_for_status" = "true"
 341                                                         device ref usb2_port6 on end
 342                                                 end
 343                                         end
 344                                 end
 345                         end
 346                         device ref acp on
 347                                 chip drivers/amd/i2s_machine_dev
 348                                         register "hid" = ""AMDI1019""
 349                                         device generic 0.0 hidden end
 350                                 end
 351                         end # Audio
 352                 end
 353
 354                 device ref lpc_bridge on
 355                         chip ec/google/chromeec
 356                                 device pnp 0c09.0 alias chrome_ec on end
 357                         end
 358                 end
 359         end # domain
 360
 361         device ref i2c_3 hidden
 362                 chip drivers/i2c/tpm
 363                         register "hid" = ""GOOG0005""
 364                         register "desc" = ""Cr50 TPM""
 365                         register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_85)"
 366                         register "power_managed_mode" = "CONFIG(PSP_S0I3_RESUME_VERSTAGE) ?
 367                                                          TPM_KERNEL_POWER_MANAGED : TPM_DEFAULT_POWER_MANAGED"
 368                         device i2c 50 alias cr50 on end
 369                 end
 370         end
 371
 372         device ref uart_0 on end # UART0
 373
 374         # See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard/guybrush/baseboard.c;l=221
 375         # for the EC configuration.
 376         #
 377         # EC is configured to power off the system at 105C, so add a two degree
 378         # buffer so the OS can gracefully shutdown.
 379         #
 380         # EC is configured to assert PROCHOT at 100C. That drastically lowers
 381         # performance. Instead we will tell the OS to start throttling the CPUs
 382         # at 95C in hopes that we don't hit the PROCHOT limit.
 383         #
 384         # We set use_acpi1_thermal_zone_scope because the Chrome ec.asl
 385         # performs a `Notify` to the `_\TZ` scope.
 386         chip drivers/acpi/thermal_zone
 387                 register "description" = ""SOC""
 388                 use chrome_ec as temperature_controller
 389                 register "sensor_id" = "0"
 390                 register "polling_period" = "10"
 391                 register "critical_temperature" = "103"
 392                 register "passive_config.temperature" = "95"
 393                 register "use_acpi1_thermal_zone_scope" = "true"
 394
 395                 device generic 0 on end
 396         end
 397         chip drivers/acpi/thermal_zone
 398                 register "description" = ""Charger""
 399                 use chrome_ec as temperature_controller
 400                 register "sensor_id" = "1"
 401                 register "polling_period" = "10"
 402                 register "critical_temperature" = "103"
 403                 register "passive_config.temperature" = "95"
 404                 register "use_acpi1_thermal_zone_scope" = "true"
 405
 406                 device generic 1 on end
 407         end
 408         chip drivers/acpi/thermal_zone
 409                 register "description" = ""Memory""
 410                 use chrome_ec as temperature_controller
 411                 register "sensor_id" = "2"
 412                 register "polling_period" = "10"
 413                 register "critical_temperature" = "103"
 414                 register "passive_config.temperature" = "95"
 415                 register "use_acpi1_thermal_zone_scope" = "true"
 416
 417                 device generic 2 on end
 418         end
 419         chip drivers/acpi/thermal_zone
 420                 register "description" = ""CPU""
 421                 use chrome_ec as temperature_controller
 422                 register "sensor_id" = "3"
 423                 register "polling_period" = "10"
 424                 register "critical_temperature" = "103"
 425                 register "passive_config.temperature" = "95"
 426                 register "use_acpi1_thermal_zone_scope" = "true"
 427
 428                 device generic 3 on end
 429         end
 430 end     # chip soc/amd/cezanne