src/mainboard/google/guybrush/variants/nipperkin/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <boardid.h>
   6 #include <gpio.h>
   7
   8 /* This table is used by nipperkin variant with board version < 2. */
   9 static const struct soc_amd_gpio bid1_override_gpio_table[] = {
  10         /* Unused TP1056 */
  11         PAD_NC(GPIO_4),
  12         /* Unused TP1063 */
  13         PAD_NC(GPIO_17),
  14         PAD_NC(GPIO_18),
  15         /* LCD_PRIVACY_PCH */
  16         PAD_GPO(GPIO_5, HIGH),
  17         /* GSC_SOC_INT_L */
  18         PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
  19         /* Unused */
  20         PAD_NC(GPIO_85),
  21         /* EN_PWR_FP */
  22         PAD_GPO(GPIO_32, LOW),
  23         /* EN_SPKR */
  24         PAD_GPO(GPIO_31, HIGH),
  25         /* Unused TP27 */
  26         PAD_NC(GPIO_70),
  27 };
  28
  29 /* This table is used by nipperkin variant with board version >= 2. */
  30 static const struct soc_amd_gpio bid2_override_gpio_table[] = {
  31         /* Unused TP1056 */
  32         PAD_NC(GPIO_4),
  33         /* Unused TP1063 */
  34         PAD_NC(GPIO_17),
  35         /* LCD_PRIVACY_PCH */
  36         PAD_GPO(GPIO_18, HIGH),
  37         /* SOC_SC_PWRSV */
  38         PAD_GPO(GPIO_31, HIGH),
  39         /* WWAN_DPR_SAR_ODL */
  40         PAD_GPO(GPIO_42, HIGH),
  41 };
  42
  43 static const struct soc_amd_gpio override_early_gpio_table[] = {
  44         PAD_NC(GPIO_18),
  45         /* BID==1: EN_SPKR to select RAM_ID input, BID >= 1: Unused in later stages */
  46         PAD_GPO(GPIO_31, LOW),
  47 };
  48
  49 static const struct soc_amd_gpio override_romstage_gpio_table[] = {
  50         PAD_NC(GPIO_18),
  51 };
  52
  53
  54 /* This table is used by nipperkin variant with board version < 2. */
  55 static const struct soc_amd_gpio bid1_tpm_gpio_table[] = {
  56         /* I2C3_SCL */
  57         PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
  58         /* I2C3_SDA */
  59         PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
  60         /* GSC_SOC_INT_L */
  61         PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
  62 };
  63
  64 /* This table is used by nipperkin variant with board version >= 2. */
  65 static const struct soc_amd_gpio bid2_tpm_gpio_table[] = {
  66         /* I2C3_SCL */
  67         PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
  68         /* I2C3_SDA */
  69         PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
  70         /* GSC_SOC_INT_L */
  71         PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
  72 };
  73
  74 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
  75 {
  76         uint32_t board_version = board_id();
  77
  78         if (board_version < 2) {
  79                 *size = ARRAY_SIZE(bid1_override_gpio_table);
  80                 return bid1_override_gpio_table;
  81         }
  82
  83         *size = ARRAY_SIZE(bid2_override_gpio_table);
  84         return bid2_override_gpio_table;
  85 }
  86
  87 const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
  88 {
  89         *size = ARRAY_SIZE(override_early_gpio_table);
  90         return override_early_gpio_table;
  91 }
  92
  93 const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size)
  94 {
  95         *size = ARRAY_SIZE(override_romstage_gpio_table);
  96         return override_romstage_gpio_table;
  97 }
  98
  99 const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size)
 100 {
 101         uint32_t board_version = board_id();
 102
 103         if (board_version < 2) {
 104                 *size = ARRAY_SIZE(bid1_tpm_gpio_table);
 105                 return bid1_tpm_gpio_table;
 106         }
 107
 108         *size = ARRAY_SIZE(bid2_tpm_gpio_table);
 109         return bid2_tpm_gpio_table;
 110 }