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soc/intel/{mtl,ptl,tgl}: Fix incorrect reporting of S0ix
[coreboot.git] / src / mainboard / google / guybrush / variants / nipperkin / overridetree.cb
blob02444aa59ac77763840ea54b288d17a02e78796a
1 # SPDX-License-Identifier: GPL-2.0-or-later
2 fw_config
3 field KB_BL 0
4 option KB_BL_ABSENT 0
5 option KB_BL_PRESENT 1
6 end
7 field FP 1
8 option FP_ABSENT 0
9 option FP_PRESENT 1
10 end
11 field WLAN 2 3
12 option WLAN_WCN6856 0
13 option WLAN_RTL8852 1
14 end
15 field WWAN 4 5
16 option WWAN_DIASABLED 0
17 option WWAN_L850GL 1
18 end
19 field STORAGE 6
20 option STORAGE_EMMC 0
21 option STORAGE_SSD 1
22 end
23 field KB_MAP 7
24 option KB_MAP_PRIVACY 0
25 option KB_MAP_NO_PRIVACY 1
26 end
27 end
28
29 chip soc/amd/cezanne
30
31 register "usb_phy_custom" = "true"
32 register "usb_phy" = "{
33 /* Left USB C0 Port */
34 .Usb2PhyPort[0] = {
35 .compdstune = 5,
36 .sqrxtune = 3,
37 .txfslstune = 3,
38 .txpreempamptune = 1,
39 .txpreemppulsetune = 0,
40 .txrisetune = 1,
41 .txvreftune = 9,
42 .txhsxvtune = 3,
43 .txrestune = 1,
44 },
45 /* Left USB A0 Port or WWAN */
46 .Usb2PhyPort[1] = {
47 .compdstune = 5,
48 .sqrxtune = 3,
49 .txfslstune = 3,
50 .txpreempamptune = 1,
51 .txpreemppulsetune = 0,
52 .txrisetune = 1,
53 .txvreftune = 9,
54 .txhsxvtune = 3,
55 .txrestune = 1,
56 },
57 /* User facing camera */
58 .Usb2PhyPort[2] = {
59 .compdstune = 1,
60 .sqrxtune = 3,
61 .txfslstune = 3,
62 .txpreempamptune = 2,
63 .txpreemppulsetune = 0,
64 .txrisetune = 2,
65 .txvreftune = 3,
66 .txhsxvtune = 3,
67 .txrestune = 2,
68 },
69 /* World facing camera */
70 .Usb2PhyPort[3] = {
71 .compdstune = 1,
72 .sqrxtune = 3,
73 .txfslstune = 3,
74 .txpreempamptune = 2,
75 .txpreemppulsetune = 0,
76 .txrisetune = 2,
77 .txvreftune = 3,
78 .txhsxvtune = 3,
79 .txrestune = 2,
80 },
81 /* Right USB C1 Port */
82 .Usb2PhyPort[4] = {
83 .compdstune = 6,
84 .sqrxtune = 3,
85 .txfslstune = 3,
86 .txpreempamptune = 1,
87 .txpreemppulsetune = 0,
88 .txrisetune = 1,
89 .txvreftune = 0xe,
90 .txhsxvtune = 3,
91 .txrestune = 1,
92 },
93 /* Right USB A1 Port */
94 .Usb2PhyPort[5] = {
95 .compdstune = 5,
96 .sqrxtune = 3,
97 .txfslstune = 3,
98 .txpreempamptune = 1,
99 .txpreemppulsetune = 0,
100 .txrisetune = 1,
101 .txvreftune = 9,
102 .txhsxvtune = 3,
103 .txrestune = 1,
104 },
105 /* WiFi / Bluetooth */
106 .Usb2PhyPort[6] = {
107 .compdstune = 1,
108 .sqrxtune = 3,
109 .txfslstune = 3,
110 .txpreempamptune = 2,
111 .txpreemppulsetune = 0,
112 .txrisetune = 2,
113 .txvreftune = 3,
114 .txhsxvtune = 3,
115 .txrestune = 2,
116 },
117 /* Smart Card */
118 .Usb2PhyPort[7] = {
119 .compdstune = 1,
120 .sqrxtune = 3,
121 .txfslstune = 3,
122 .txpreempamptune = 2,
123 .txpreemppulsetune = 0,
124 .txrisetune = 2,
125 .txvreftune = 3,
126 .txhsxvtune = 3,
127 .txrestune = 2,
128 },
129 /* Left USB C0 Port */
130 .Usb3PhyPort[0] = {
131 .tx_term_ctrl=2,
132 .rx_term_ctrl=2,
133 .tx_vboost_lvl_en=1,
134 .tx_vboost_lvl=5,
135 },
136 /* Left USB A0 Port or WWAN */
137 .Usb3PhyPort[1] = {
138 .tx_term_ctrl=2,
139 .rx_term_ctrl=2,
140 .tx_vboost_lvl_en=1,
141 .tx_vboost_lvl=5,
142 },
143 /* Right USB C1 Port */
144 .Usb3PhyPort[2] = {
145 .tx_term_ctrl=2,
146 .rx_term_ctrl=2,
147 .tx_vboost_lvl_en=1,
148 .tx_vboost_lvl=5,
149 },
150 /* Right USB A1 Port */
151 .Usb3PhyPort[3] = {
152 .tx_term_ctrl=2,
153 .rx_term_ctrl=2,
154 .tx_vboost_lvl_en=1,
155 .tx_vboost_lvl=5,
156 },
157 .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
158 .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
159 .BatteryChargerEnable = 0,
160 .PhyP3CpmP4Support = 0,
161 }"
162
163 device domain 0 on
164 device ref gpp_bridge_2 on
165 # Required so the NVMe gets placed into D3 when entering S0i3.
166 chip drivers/pcie/rtd3/device
167 register "name" = ""NVME""
168 device pci 00.0 on end
169 end
170 probe STORAGE STORAGE_EMMC
171 end # EMMC
172 device ref gpp_bridge_3 on
173 # Required so the NVMe gets placed into D3 when entering S0i3.
174 chip drivers/pcie/rtd3/device
175 register "name" = ""NVME""
176 device pci 00.0 on end
177 end
178 probe STORAGE STORAGE_SSD
179 end # NVMe
180 device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
181 device ref gfx on
182 chip drivers/gfx/generic
183 register "device_count" = "1"
184 register "device[0].name" = ""LCD""
185 # Use ChromeOS privacy screen _HID
186 register "device[0].hid" = ""GOOG0010""
187 # Internal panel on the first port of the graphics chip
188 register "device[0].type" = "panel"
189 register "device[0].privacy.enabled" = "1"
190 register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_18)"
191 device generic 0.0 on
192 probe KB_MAP KB_MAP_PRIVACY
193 end
194 end
195 end
196 device ref acp on
197 chip drivers/amd/i2s_machine_dev
198 register "hid" = ""10029836""
199 device generic 0.0 hidden end
200 end
201 end # Audio
202 device ref xhci_1 on # USB 3.1 (USB1)
203 chip drivers/usb/acpi
204 device ref xhci_1_root_hub on
205 chip drivers/usb/acpi # Bluetooth
206 register "enable_off_delay_ms" = "10"
207 device ref usb2_port6 on end
208 end
209 end
210 end
211 end
212 end
213 end # domain
214
215 register "slow_ppt_limit_mW" = "25000"
216 register "fast_ppt_limit_mW" = "30000"
217 register "slow_ppt_time_constant_s" = "5"
218 register "stapm_time_constant_s" = "275"
219 register "sustained_power_limit_mW" = "12000"
220 register "thermctl_limit_degreeC" = "100"
221
222 register "telemetry_vddcrvddfull_scale_current_mA" = "94623" #mA
223 register "telemetry_vddcrvddoffset" = "1847"
224 register "telemetry_vddcrsocfull_scale_current_mA" = "29904" #mA
225 register "telemetry_vddcrsocoffset" = "756"
226
227 # Enable STT support
228 register "stt_control" = "1"
229 register "stt_pcb_sensor_count" = "2"
230 register "stt_min_limit" = "12000"
231 register "stt_m1" = "0x04DE"
232 register "stt_m2" = "0x13"
233 register "stt_m3" = "0"
234 register "stt_m4" = "0"
235 register "stt_m5" = "0"
236 register "stt_m6" = "0"
237 register "stt_c_apu" = "0xDA43"
238 register "stt_c_gpu" = "0"
239 register "stt_c_hs2" = "0"
240 register "stt_alpha_apu" = "0x199A"
241 register "stt_alpha_gpu" = "0"
242 register "stt_alpha_hs2" = "0"
243 register "stt_skin_temp_apu" = "0x2E00"
244 register "stt_skin_temp_gpu" = "0"
245 register "stt_skin_temp_hs2" = "0"
246 register "stt_error_coeff" = "0x21"
247 register "stt_error_rate_coefficient" = "0x2666"
248
249 # I2C Config
250 #+-------------------+---------------------------+
251 #| Field | Value |
252 #+-------------------+---------------------------+
253 #| I2C0 | Trackpad |
254 #| I2C1 | Touchscreen |
255 #| I2C2 | Speaker, Codec, P-SAR |
256 #| I2C3 | H1 TPM |
257 #+-------------------+---------------------------+
258 register "i2c[0]" = "{
259 .speed = I2C_SPEED_FAST,
260 }"
261
262 register "i2c[1]" = "{
263 .speed = I2C_SPEED_FAST,
264 }"
265
266 register "i2c[2]" = "{
267 .speed = I2C_SPEED_FAST,
268 }"
269
270 register "i2c[3]" = "{
271 .speed = I2C_SPEED_FAST,
272 .early_init = true,
273 }"
274
275 register "edp_phy_override" = "1"
276
277 # bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2, bit3=1: DP3
278 register "edp_physel" = "0x1"
279
280 register "edp_tuningset" = "{
281 .dp_vs_pemph_level = 0x00,
282 .tx_eq_main = 0x1f,
283 .tx_eq_pre = 0x0,
284 .tx_eq_post = 0x0,
285 .tx_vboost_lvl = 0x5,
286 }"
287
288 device ref i2c_0 on
289 chip drivers/i2c/generic
290 register "hid" = ""ELAN0000""
291 register "desc" = ""ELAN Touchpad""
292 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
293 register "wake" = "GEVENT_22"
294 register "detect" = "1"
295 device i2c 15 on end
296 end
297 end # I2C0
298
299 device ref i2c_1 on
300 chip drivers/i2c/generic
301 register "hid" = ""ELAN0001""
302 register "desc" = ""ELAN Touchscreen""
303 register "detect" = "1"
304 register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_89)"
305 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_68)"
306 register "enable_delay_ms" = "1"
307 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_121)"
308 register "reset_delay_ms" = "20"
309 register "has_power_resource" = "true"
310 device i2c 10 on end
311 end
312 chip drivers/i2c/hid
313 register "generic.hid" = ""GTCH7503""
314 register "generic.desc" = ""G2TOUCH Touchscreen""
315 register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_89)"
316 register "generic.detect" = "1"
317 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_68)"
318 register "generic.enable_delay_ms" = "1"
319 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_121)"
320 register "generic.reset_delay_ms" = "50"
321 register "generic.has_power_resource" = "1"
322 register "hid_desc_reg_offset" = "0x01"
323 device i2c 40 on end
324 end
325 end # I2C1
326
327 device ref i2c_2 on
328 chip drivers/i2c/generic
329 register "hid" = ""RTL5682""
330 register "name" = ""RT58""
331 register "desc" = ""Realtek RT5682""
332 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)"
333 register "property_count" = "1"
334 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
335 register "property_list[0].name" = ""realtek,jd-src""
336 register "property_list[0].integer" = "1"
337 device i2c 1a on end
338 end
339 end # I2C2
340
341 device ref uart_1 on
342 chip drivers/uart/acpi
343 register "name" = ""CRFP""
344 register "desc" = ""Fingerprint Reader""
345 register "hid" = "ACPI_DT_NAMESPACE_HID"
346 register "compat_string" = ""google,cros-ec-uart""
347 register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_21)"
348 register "wake" = "GEVENT_5"
349 register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
350 register "has_power_resource" = "true"
351 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_11)"
352 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_3)"
353 register "enable_delay_ms" = "3"
354 device generic 0 alias fpmcu on
355 probe FP FP_PRESENT
356 end
357 end
358 end
359
360 chip drivers/generic/max98357a
361 register "hid" = ""MX98360A""
362 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_70)"
363 register "sdmode_delay" = "5"
364 device generic 0.1 on end
365 end
366
367 end # chip soc/amd/cezanne
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