src/mainboard/google/hatch/variants/helios/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/variants.h>
   4 #include <baseboard/gpio.h>
   5 #include <boardid.h>
   6 #include <gpio.h>
   7 #include <soc/cnl_memcfg_init.h>
   8 #include <string.h>
   9 #include <variant/gpio.h>
  10
  11 static const struct cnl_mb_cfg baseboard_memcfg = {
  12         /*
  13          * The dqs_map arrays map the SoC pins to the lpddr3 pins
  14          * for both channels.
  15          *
  16          * "The index of the array is CPU byte number, the values are DRAM byte
  17          * numbers." - doc #573387
  18          *
  19          * the index = pin number on SoC
  20          * the value = pin number on lpddr3 part
  21          */
  22         .dqs_map[DDR_CH0] = {4, 7, 5, 6, 0, 3, 2, 1},
  23         .dqs_map[DDR_CH1] = {0, 3, 2, 1, 4, 7, 6, 5},
  24
  25         .dq_map[DDR_CH0] = {
  26                 {0xf0, 0xf},
  27                 {0x0, 0xf},
  28                 {0xf0, 0xf},
  29                 {0xf0, 0x0},
  30                 {0xff, 0x0},
  31                 {0xff, 0x0}
  32         },
  33         .dq_map[DDR_CH1] = {
  34                 {0xf, 0xf0},
  35                 {0x0, 0xf0},
  36                 {0xf, 0xf0},
  37                 {0xf, 0x0},
  38                 {0xff, 0x0},
  39                 {0xff, 0x0}
  40         },
  41
  42         /* Helios uses 200, 80.6 and 162 rcomp resistors */
  43         .rcomp_resistor = {200, 81, 162},
  44
  45         /* Helios Rcomp target values */
  46         .rcomp_targets = {100, 40, 40, 23, 40},
  47
  48         /* Set CaVref config to 0 for LPDDR3 */
  49         .vref_ca_config = 0,
  50
  51         /* Disable Early Command Training */
  52         .ect = 0,
  53 };
  54
  55 void variant_memory_params(struct cnl_mb_cfg *bcfg)
  56 {
  57         memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
  58 }
  59
  60 int variant_memory_sku(void)
  61 {
  62         const gpio_t spd_gpios[] = {
  63                 GPIO_MEM_CONFIG_0,
  64                 GPIO_MEM_CONFIG_1,
  65                 GPIO_MEM_CONFIG_2,
  66                 GPIO_MEM_CONFIG_3,
  67         };
  68
  69         int val = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
  70
  71         if ((board_id() != 0) && (board_id() != BOARD_ID_UNKNOWN))
  72                 return val;
  73
  74         /*
  75          * For boards with id 0 or unknown, memory straps 3 and 4 are
  76          * incorrectly stuffed in hardware. This is a workaround for these
  77          * boards to override memory strap 3 to 0 and 4 to 1.
  78          */
  79         switch (val) {
  80         case 3:
  81                 val = 0;
  82                 break;
  83         case 4:
  84                 val = 1;
  85                 break;
  86         }
  87
  88         return val;
  89 }